Scientists in Japan have built a new transistor that can withstand temperatures of 1,110 degrees Fahrenheit (600 degrees Celsius). Components this robust could one day be used in surface probes on Venus — where the thick carbon dioxide atmosphere can reach temperatures of 860 F (460 C).

Most modern tech, including instruments used for deep-space exploration, uses transistors to control the flow of current. But the new device is a type of junction field-effect transistor (JFET), where the strength of an electrical field changes the channel’s conductivity.

JFETs are typically used in specialist applications because they are more difficult to scale down than the more common metal-oxide-semiconductor field-effect transistors (MOSFETs), which are widely used in consumer smartphones and computers. But JFETs can offer lower noise levels because their operation does not rely on an oxide layer, which can introduce interference.

The researchers outlined how the new transistor works in a study published Aug. 17 in the journal APL Electronic Devices.

Can't take the heat

Since at least the start of the century, silicon carbide (SiC) JFETs have been considered a promising option for low-power integrated circuits heading for Venus due to the material's inherent ability to withstand high temperatures.

As the scientists pointed out in the new study: "Past landers have been limited to only a few hours by silicon-based electronics." Venera 13, a Soviet-era lander, holds the world record for the longest time survived on Venus by a spacecraft, at 2 hours, 7 minutes.

"Integrated circuits (ICs) fabricated with SiC are particularly attractive for extreme environments, such as deep-space exploration, geothermal drilling, and aerospace engine control, where conventional silicon-based ICs cannot operate reliably," the researchers added.

But recently developed SiC-JFETs have all met the same two problems: low controllability and large leakage currents. The former is linked to how the SiC substrate is doped with other atoms to alter its electrical properties, defining its gate (where the electrical field is created) and channel (where the current flows) regions.

In a material with a regular crystal structure, like SiC, some dopant atoms may penetrate deeper than expected. This doesn't matter under normal conditions, but when exposed to high temperatures, it causes variations in the field voltage required to open the channel and makes the transistor harder to control reliably. The scientists found that it can throw conventional JFET voltage thresholds off by over 2 volts.

Furthermore, at temperatures above 660 F (350 C), the SiC substrate can become less electrically resistive, allowing current to flow even when the transistor is switched off. This makes it harder for the JFET to control current properly, potentially causing incorrect signals and increased power consumption.

Even the highest-performing JFETs can only operate long-term at 930 F (500 C), but the Kyoto team had a theory as to why these challenges remained unresolved.

"We believe the lack of development is because the research community has been trying to apply silicon-era thinking to a fundamentally different material," said first author of the study Mitsuaki Kaneko, associate professor of engineering at Kyoto University, in a statement.

Turning the transistor on its head

The researchers designed their new SiC-JFET with these two challenges in mind. To improve controllability, they implemented a bottom-gate structure, where the gate is positioned underneath the SiC conducting channel.

Its gate region is heavily doped by design, so when dopant atoms in the channel penetrate deeper into the SiC, it doesn't change the overall doping profile of the channel-gate region, limiting its impact on the threshold voltage even at high temperatures.

The team also used dopants to create two semiconductor regions, or "wells", in the SiC around the JFET. The boundaries between the wells act as barriers to current flow, meaning that even when the SiC becomes more conductive at high temperatures, current cannot bypass the channel when the transistor is switched off.

Researchers measured how well the new JFET could switch current on and off and how closely the actual threshold voltage matched the theoretical value, based on its thickness and level of doping. They recorded these metrics at temperatures ranging from room temperature to 1,110 F (600 C).

"The fabricated devices demonstrated stable, normal transistor operation at temperatures over 873 K [1,110°F], opening up possibilities for ultrahigh-temperature SiC devices," they wrote in the study. Furthermore, at about 750 F (400 C), the threshold-voltage error was found to be less than 0.1 V thanks to the bottom-gate design.

As well as surface probes on Venus, the transistor could be useful inside jet engines, the scientists said. Currently, components connected to gas turbines must be protected from extreme temperatures using thermal shielding, long wires and energy-intensive cooling systems, restricting engine design.

Before it can be launched into space or hooked up to a plane, the team still needs to test and optimise the transistor for practical use. This includes integrating it into more complex circuits, scaling it up to wafer-level and ensuring that the entire circuit package will withstand extreme temperatures and pressures.

Indeed, it may not be too lofty a goal. NASA demonstrated that integrated circuits with SiC-JFETs could withstand temperatures of 860 F (460 C) and 9.3 MPa of pressure for 60 days, and 930°F (500 C) in the air for over a year. Plus, in 2024, a team from the National Institute for Materials Science in Japan developed a MOSFET out of diamond that could operate above 570 F (300 C).

For decades, engineers have been working to create smaller and smaller transistors to fit ever-larger numbers of them onto computer chips, all in the name of greater processing power. Now, in the age of artificial intelligence (AI), that effort has turned into an all-out race.

So how small can a transistor actually get? And is smaller even still the goal?

To understand the answer, first you need to know what a transistor is.

"If you take a computer or your mobile phone and you were to pry it open, you will see that there is a printed circuit board," Suman Datta, a professor of electrical and computer engineering at Georgia Tech, told Live Science.

On that circuit board are small, rectangular objects called chips, and inside each chip is a tiny piece of silicon. "And in that silicon, if you zoom in like a million times … maybe, if you're lucky, you will start seeing these tiny switches or transistors sitting etched into that piece of silicon," Datta said.

Each transistor is effectively a switch that turns on and off in response to jolts of electricity pulsing 4 billion times per second. Modern devices contain billions of transistors, and each one turning on and off in a precise orchestration to move and store 1s and 0s powers everything from Google searches and AI data centers to the device you're using to read these words.

The smaller the transistors are, the more can fit on each chip and the greater the chip's speed and functionality. So how small have they gotten so far?

"Researchers have built proof-of-concept devices in which a single atom controls the flow of electrons, although the rest of the device is still much larger," Anton Persson, an assistant professor at Chalmers University of Technology in Sweden, and Tara Peña, an incoming assistant professor at UCLA, told Live Science via a jointly written email. That means the switching part of a transistor has been made at the smallest scale physically possible, even though a complete device that small doesn't exist yet. New materials and approaches could make these devices even smaller. In a study published in June in the journal Nature Nanotechnology, Persson, Peña and colleagues used two-dimensional semiconductors made of tungsten disulfide, among other materials, to shrink nanoribbon transistors down to a channel width of 25 nanometers ‪—‬ about 0.00025 the width of a human hair.

Two-dimensional semiconductors are electrically active materials that are only one or a few atoms thick, and because electrical current can be controlled more precisely in such a thin layer, they allow for smaller transistors than traditional silicon does.

Over the next decade, they still expect silicon transistors to shrink, but more slowly than they did in the past, they said. "To go considerably smaller, we may eventually need to move beyond silicon to atomically thin materials, such as the two-dimensional semiconductors we study."

A host of considerations

Size isn't the only consideration; cost is important, too. It's enormously expensive up front to design and build a new chip. "We are as R&D-intensive as drug companies that spend billions of dollars developing one drug," Datta said. "It's a very similar business model."

There are also manufacturing factors to consider. "The often much harder step is producing billions of those transistors reliably, at scale and at a price that makes sense commercially," Persson and Peña said. "Something that works once in a laboratory does not necessarily work in a factory."

Another consideration is energy efficiency. "If I'm adding more and more transistors onto that little piece of silicon, and at the individual transistor level, they don't become more energy efficient … then when I go from, let's say, 10 transistors to 20 transistors, my power budget has to be doubled, all things being equal," Datta said.

For example, the latest Nvidia data center GPUs consume 1.4 kilowatts of electricity, and Nvidia's upcoming release is estimated to consume nearly a kilowatt more than that. Half of that is given up as waste heat, Datta said.

"So it's not just smaller, faster, cheaper, but also more energy efficient," Datta said. "You have to work on all the four vectors."

Is smaller still the goal in the age of AI?

Still, there is a limit to the physical space available for additional transistors, which is why engineers are turning to 3D designs — think taller instead of smaller.

"Instead of only making each transistor smaller, the idea is increasingly to stack transistors on top of one another so that more of them fit within the same chip area," Persson and Peña said. "That way, we can still make our electronics considerably more powerful, even if each transistor shrinks only modestly."

The quest for faster, more efficient chips is only getting more urgent with the explosive growth of AI. But smaller transistors and more powerful chips aren't just important for AI data centers; they also mean smaller, potentially cheaper consumer electronics.

"People certainly notice the consequences of smaller transistors," Persson and Peña said. "They can use less power and allow more computing power to fit on the same chip. That can mean faster electronics, longer battery life and lower costs. Historically, that combination has enabled today's smartphones to outperform room-sized supercomputers from decades ago."

So how small can transistors get? "We will do everything to make it as small as possible as long as we can control the physics," Datta said. "And as long as we can, we will find a way to make the economics work."

Photovoltaic technology, most commonly seen as the bulky solar panels used on solar farms, is expected to become a dominant energy source by 2050. But these panels are often installed on land that might otherwise be used to grow crops for feeding a burgeoning population.

Agrivoltaics aims to solve this problem by planting crops around or underneath rows of solar panels, allowing for more efficient land use. In previous studies, solar panels were shown to help shade and protect certain crops as well as increase soil moisture, suggesting that carefully designed systems could support both agriculture and clean energy production.

Existing agrivoltaic research, however, tends to focus on one aspect of this process at a time — for example, light availability or crop growth — rather than addressing the nuanced interactions between microclimates, crop type, light, and panel type. Hosseini et al. share a new model that can simulate the microclimates beneath solar panels and even addresses the heat stress that workers might face in actual conditions.

The new model simulates the interactions between solar panels, crops, soil, air and water movement, and carbon dioxide uptake by tracking how energy, momentum, and mass move through the agrivoltaic system. The researchers used agrivoltaic site data, including leaf temperature measurements taken in Davis, Calif., and soil temperatures taken in Chicago City, Minn., to assess how the model's efforts matched real-world conditions.

They then applied the model to a hypothetical agrivoltaic tomato farm using weather data from a hot, humid day in Princeton, N.J., a representative location for the densely populated mid-Atlantic region, where food and energy are both in high demand.

Compared to tomatoes grown in an open field, tomatoes grown under solar panels experienced leaf temperatures that were 1.84°C cooler during the day overall and up to 7.56°C cooler during peak afternoon heat, reducing water loss through evapotranspiration by 22.4%. Even though the simulated crops received 47% less sunlight, their carbon uptake declined by only 31%, suggesting that more temperate conditions lowered heat stress and partially offset the effects of increased shade.

The solar panels themselves were also 5.6°C cooler during the daytime than panels in bare soil, allowing them to recover about 15% of the efficiency that is lost during hotter temperatures. The average perceived temperatures for humans decreased by 4.46°C during working hours, implying important occupational health and safety benefits for farmworkers. The researchers suggest this model can be used to examine the benefits of agrivoltaic farms as well as other climate and crop combinations.

Scientists have developed a new type of artificial intelligence (AI) chip that mimics the human brain's aptitude for instinctive motor responses.

Modeled after the cerebellum, the part of the brain that helps coordinate balance and fine muscle control, the chip is designed to ignore routine information and respond only to unexpected events.

In simulated tests using electrocardiogram (ECG) data, the device flagged irregular heartbeats (arrhythmias) within one-fifth of a heartbeat and with 98% accuracy, according to the researchers — and did so twice as fast as conventional AI systems. The team published their findings July 10 in the journal Nature Communications.

The device could pave the way for highly responsive, low-power AI systems capable of spotting and reacting to unusual events without relying on the massive computing resources of data centers — from always-on health monitors to self-driving cars and autonomous robots.

A new approach to neuromorphic computing

Computer architecture inspired by the human brain is known as neuromorphic computing. Many researchers consider it key to developing more advanced and efficient AI systems, because it more closely mimics how neurons fire in the human brain.

Rather than processing all incoming information with equal intensity, the brain's biological circuits prioritize important signals and filter out routine background noise, helping it conserve energy.

Most neuromorphic approaches focus on the cerebrum, the largest part of the human brain and the central "thought center." In the new study, the scientists instead focused on the cerebellum, a smaller brain region responsible for coordination and instinctive motor skills — things we do without much conscious thought.

Neural circuits in the cerebellum contain competing excitatory and inhibitory signals that normally balance each other out. When something unexpected happens, the balance shifts and alerts the brain that it needs to react.

This makes the cerebellum a prime, untapped candidate for neuromorphic AI systems, said study co-author Mark Hersam, a professor of materials science and engineering at Northwestern University.

"The cerebellum is excellent at ignoring the expected and reserving its resources for reacting to the unexpected," Hersam said in a statement. "That approach ultimately translates into lower energy consumption."

Merging memory and compute

While current AI is exceptionally good at recognizing patterns, it spends enormous amounts of computing power continuously analyzing streams of data.

One of the constraints is the hardware itself. Processing information involves shuttling data back and forth between separate memory and processing components, resulting in a delay known as the von Neumann bottleneck.

This new device integrates memory and processing into a single component called a memtransistor (a portmanteau of "memory" and "transistor"), enabling it to move data much more quickly and efficiently.

The memtransistor is made from an atomically thin semiconductor called molybdenum disulfide, which forms a channel between two electrodes. One electrode makes direct contact with the semiconductor, while the other sits partly above it, separated by a thin insulating layer.

This asymmetry changes how electricity flows through the device, allowing it to switch between "excitatory" and "inhibitory" modes when the direction of the voltage is reversed, the researchers explained in the study.

The "output layer" of spiking neural networks

The device is designed to form the core of the output layer of a larger spiking neural network (SSN), Hersam explained in an email to Live Science.

SNNs are a type of neural network that processes information as a series of electrical spikes, mimicking how signals pass between neurons. For the study, the researchers measured how individual memtransistors responded to repeated electrical pulses, then used the results to simulate a network comprising multiple devices that could distinguish normal ECG patterns from arrhythmias.

They then fed the same ECG data into the cerebellum-inspired memtransistor network and a standard transformer model — the AI architecture that underpins large language models (LLMs) — and compared how quickly and efficiently each detected an arrhythmia. The cerebellum-inspired system was more than twice as fast and required around 10,000 times fewer computer calculations, according to the team.

Hersam said the results should translate into faster, more energy-efficient hardware, though he added that real-world performance would depend on the speed and size of the devices.

"We have not scaled memtransistors to the level of commercial Si [silicon] chips, but in principle, 2D materials and memtransistors can be scaled to comparable sizes and operating speeds," he told Live Science.

More efficient AI at the edge

Hersam said the new device was particularly suited to scenarios where quick inference was needed using minimal power. "One example could be edge computing, or in cases where access to the cloud is not available or is not desired due to the sensitivity of the data," he added.

A huge potential benefit of the technology is that it could slash AI's reliance on data centers. According to the International Energy Agency, global data center electricity demand could reach around 945 terawatt-hours by 2030 — slightly more than the entire electricity consumption of Japan — largely driven by AI. One terawatt-hour is equal to 1 trillion watt-hours — enough electricity to power a 60-watt lightbulb continuously for 1.9 million years.

A hypothetical future memtransistor-based network could enable robots, autonomous vehicles and cybersecurity systems to run continuously at low power by processing data locally and reacting only when they detect an unexpected, potentially hazardous event, the researchers said.

"The current AI deployed in cybersecurity and autonomous vehicles uses the massive computing power of data centers or an in-house facility of GPUs and CPUs," Hersam told Live Science. "In contrast, our approach promises low energy/power consumption by simplifying the net number of operations needed… [This] is not an incremental performance improvement, but a fundamentally different way of detecting anomalies."

The next stage of research will focus on mimicking the cerebellum's ability to adapt to predictability ‪—‬ specifically, how the human brain stops treating events as unique or unexpected when they're encountered multiple times.

See how much you know about the most complex organ in the human body with our brain quiz!

The massive hardware demands of artificial intelligence (AI) applications are stretching the physical and structural limitations of semiconductors. But researchers have engineered a three-dimensional silicon chip that they propose as the solution.

In a new study published May 27 in the journal Nature, scientists found a way to cram more computing power into a chip by stacking silicon circuits in multiple layers in a way that doesn't impact performance.

Stacking chips vertically, known as 3D integration, is more efficient than traditional 2D chips, where silicon circuits are spread across a single surface. This is because stacking shortens the distance that data has to travel and reduces the power required for data transmission.

The researchers' 3D chip uses ultrathin silicon membranes and low-temperature manufacturing techniques to overcome the challenges of current chip architectures.

"Our method is not only easier to implement with lower cost, but it has several advantages over previous approaches to stack silicon wafers," Qing Cao, first author of the study and a materials science and engineering professor at the University of Illinois Urbana-Champaign, said in a statement.

Extending Moore's law

Since the 1960s, ensuring that electronics can handle more demanding applications has meant making transistors smaller so more can be packed onto a single chip. But, as Cao pointed out, doubling the number of transistors every couple of years — a principle known as Moore's law — is becoming less feasible.

"If you look at the actual size of transistors, they're not getting smaller, especially in terms of their contacted gate pitch," Cao said in the statement — defined as the combined width of one transistor gate and the space needed to separate it from the next.

"This is because we're becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we're going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface."

The researchers think vertical integration across multiple layers is the best way to guarantee that engineers can continue to adhere to Moore's law, because this approach creates room for more transistors on a chip.

"Today it takes six microelectronic devices called transistors on a single plane to store one bit of information," Cao explained, suggesting that just like in a densely populated city, the only way to solve overcrowding is to build upward. "You get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient."

Getting around the heat problem

Stacking is nothing new, of course, but vertical integration — building layers directly on top of one another — can create thermally dense packages. In the study, the researchers noted that the fabrication of high-quality silicon chips demands temperatures up to 1,832 degrees Fahrenheit (1,000 degrees Celsius).

However, once the first chip layer has been completed, the metal wiring introduced to connect further layers can be destroyed by such high temperatures. As a result, the "thermal budget" — the maximum amount of heat that can be endured before degradation starts to occur — for any additional layers is 752 F (400 C), said Cao. This can result in performance and reliability issues.

When creating 3D stacked silicon chips, manufacturers have sought to avoid this problem by using alternatives to single-crystalline silicon for the upper layers, according to the researchers. These materials include amorphous and nanocrystalline metal oxides, carbon nanotubes and polycrystalline silicon, but they can lead to performance and reliability issues, the scientists said in the study.

To overcome this challenge, Cao and his team adopted an approach called "monolithic integration" — a process in which all chip components are fabricated on a single piece of substrate, as opposed to making them separately and then bonding them together later.

To build each chip, the researchers created ultrathin silicon nanomembranes that they then transferred, using a roll laminator, onto a substrate containing the bottom layer.

The maximum temperature required to generate a strong bond using this method was just 392 F (200 C) — five times less than the heat normally required. The membranes they transferred were also just 10 nanometers thick or less — about the size of a protein — compared with the approximately 500-to-700-micrometer (500,000 to 700,000 nanometers) thickness of a typical wafer. Because they are thin, these membranes are mechanically flexible to conform to the underlying surface, Cao added.

The result of this process was a 3D chip with three layers, each containing 625 transistors. This pales in comparison to the billions of transistors that can be crammed onto chips already on the market, but the researchers believe their technology boasts power efficiency benefits. The electrical current that can flow through the chip has proved to be at least three to four times greater than that of monolithic chips made from alternative materials.

The big question is whether their 3D silicon chip can make the leap from the laboratory to commercial applications. While the research demonstrates the potential of a chip comprising three stacked layers, the scientists suggested that plenty more layers can be added in future iterations.

Can you match these ancient devices to their pictures? Find out with our computing quiz!

A breakthrough in photonic chips could make large, costly, ultrafast lasers dramatically smaller, leading to portable and affordable imaging, diagnostic and information-processing devices, researchers say.

By using a decades-old overlooked laser architecture, scientists managed to fit an ultrafast laser onto a tiny photonic chip — a chip that uses light, rather than electricity, for computing operations.

In a new study published June 3 in the journal Nature, the team demonstrated that a tiny laser on the photonic chip could deliver 1.05 nanojoules of energy in 147-femtosecond (147 quadrillionths of a second) bursts — thereby competing with the output of laboratory-class ultrafast lasers.

Ultrafast lasers are used in a variety of applications, from precision manufacturing and eye surgery to biological imaging and atomic clocks, but the systems needed to power them tend to take up whole tabletops in labs or factories. Yet the powerful output of these laser pulses made them difficult to miniaturise onto photonic chips.

"For more than twenty years, a high-pulse-energy femtosecond laser on chip was widely regarded as a holy grail of integrated photonics," Tobias Kippenberg, a photonics professor at the Swiss Federal Institute of Technology(EPFL), said in a statement.

"Our result shows that it is not only possible, but that it can be achieved with a surprisingly elegant architecture that the integrated-photonics community had overlooked."

Forward-thinking breakthrough comes from looking back

Photonic chips manipulate light by using microscopic structures called waveguides — usually in the form of optical fibers or etched cavities — to carry information. They aren't particularly novel, and can be found in fiber-optic communications, medical sensors and lidar systems.

But photonic chips have previously struggled when handling high-powered, ultrafast lasers. That's because they need to contain light to extremely small waveguides, leading the light to interact strongly with itself and destabilizing the laser pulses.

To tackle this problem, the researchers looked at a laser architecture called the Mamyshev oscillator, created in 1998 by Pavel V. Mamyshev, a physicist and engineer at Bell Labs.

This oscillator, which has received little attention in the world of photonic chips, works by placing a nonlinear waveguide between two optical filters. This causes a high-intensity laser pulse to expand into a broader range of colors that can then pass through both filters while weaker light, which can cause laser destabilization, is blocked out. This technique essentially means that a high-intensity laser pulse can be maintained.

Because the Mamyshev oscillator doesn't require extra components to manufacture on a chip, it presents an attractive design for use on photonic chips. And although the laser cavity needed to direct an ultrafast laser is 16.5 inches (42 centimeters) long, it can be folded to occupy around the same area as a match head. This can't be done with conventional fiber-optic-based lasers, often used in photonic chips.

That takes care of the size, but the cost of ultrafast laser systems is another challenge. But because photonic chips can be fabricated using silicon wafers in the same fashion as computer chips, more than 1,000 laser cavities could potentially be produced in a single batch, the researchers said. As such, photonic chips with ultrafast laser capabilities could be produced at scale, in turn reducing manufacturing costs and even expanding their use.

Photonic chips capable of handling ultrafast lasers could, in the future, lead to portable tools for tasks like detecting pollutants or performing advanced medical diagnostics in the field, the researchers noted in the study. The technology also opens the door to smaller atomic clocks that can benefit navigation and future communications.