OpenAI is expanding its relationship with Samsung beyond memory supply and enterprise software as the AI giant plans to outsource production of at least some of its processors to Samsung Foundry, Harrison Kim, General Manager of OpenAI Korea, revealed this week. If the information is accurate, then OpenAI will source its AI accelerators from both TSMC and Samsung Foundry, which suggests massive volume requirements.

"One of the areas where we have made the most progress and gained the most recognition with Samsung Electronics is our joint production and ​research on the next-generation chips we are developing," said Harrison Kim, General Manager of OpenAI Korea, at ​a press conference in Seoul, Reuters reports.

OpenAI already has its own AI ASIC program that relies on Broadcom's design services as well as TSMC's wafer processing and advanced packaging services. So far, the company has introduced its first inference AI accelerator called Jalapeño that was defined by the company's engineers, then co-designed with Broadcom, then made by TSMC, all in less than 18 months.

OpenAI did not explain whether Samsung's participation concerns a second production source for Jalapeño, another processor under development by OpenAI, a chip jointly developed by Samsung and OpenAI, or some other aspect of chip production and development. Samsung and SK hynix already supply memory for OpenAI's Stargate data center initiative, though joint chip development and production barely have a relation to DRAM supply.

OpenAI's 1^st Generation Jalapeño will unlikely be double-sourced from TSMC and Samsung because the chip is already in mass production at TSMC and OpenAI is talking about 'next-generation chips,' not the ones that are in mass production at the moment. Furthermore, development of Jalapeño's successor is well underway and is approaching tapeout, which means that its mass production is not far away either. Since OpenAI's claim clearly involves 'next-generation chips,' it is entirely possible that OpenAI will indeed produce its 2^nd Generation inference ASIC at Samsung Foundry.

Back in late July, Samsung Electronics and Broadcom announced a strategic partnership valued at over $200 billion through 2030 to collaborate on advanced foundry, memory, and packaging technologies for AI infrastructure. Hence, as OpenAI has an agreement with Broadcom to procure 10GW of custom AI accelerators, it will be able to produce these accelerators at both Samsung and TSMC. Of course, if it needs silicon produced at Samsung, and pays Broadcom for appropriate design porting.

Perhaps, OpenAI will take a page from Tesla's book and will double-source Jalapeño's successor from TSMC and Samsung to get higher volumes. However, Tesla's volume requirements may be different from those of OpenAI.

Tesla needs extraordinary AI5 volumes because it intends to use the processor across three very different high-volume applications: AI data centers, vehicles, and Optimus robots. Therefore, Tesla could potentially need millions of AI5 chips for cars alone, on top of robots and data-center deployments. Therefore, paying for separate TSMC and Samsung physical implementations gives Tesla not only supply-chain resilience but also aggregate capacity necessary to supply several product categories.

Yet, data center accelerators tend to be vastly more silicon-intensive per unit compared to ASICs for vehicles or robots. If OpenAI/Broadcom's next ASIC is a large leading-edge processor with multiple dies and OpenAI wants gigawatts of these processors, wafer requirements could still become too high for TSMC alone (which is fully booked by the likes of AMD and Nvidia). In that situation, OpenAI may need another foundry to get enough ASICs. Still, we are speculating.

For years, TSMC has tried to avoid making public comments about its plans to use EUV lithography with a 0.55 numerical aperture optics, or High-NA EUV, because the company's developers had a good idea how to keep advancing process technologies without using $400 million scanners. However, TSMC cannot rely on Low-NA EUV systems forever, so this week the company announced plans to use High-NA EUV starting from 2030.

TSMC did not formally reveal which fabrication technology will be the first to adopt High-NA EUV, though the year 2030 points to a few candidates. What TSMC did say is that it expects the number of layers processed using High-NA EUV to eventually increase as its fabrication technologies become more complex, driven by increasing complexity of transistor architectures, which is probably an implication for more sophisticated implementations of gate-all-around (GAA) transistors as well as complementary field-effect transistors (CFETs) later on.

TSMC plans to start using High-NA EUV lithography tools for high-volume manufacturing in 2030 using conventional 6×6-inch photomasks. The company then plans to build a pilot line that uses 6×12-inch photomasks in 2031 with the goal of bringing 6×12-inch High-NA lithography systems into advanced node production by 2033.

High-NA EUV lithography tools can achieve an 8nm single-exposure resolution, as opposed to a 13nm single-exposure resolution offered by today's Low-NA EUV litho systems. However, when used with conventional 6×6-inch photomasks, High-NA EUV scanners have only half the exposure field of their Low-NA counterparts, which creates challenges for manufacturing very large dies. As a result, chipmakers building massive AI accelerators must either stitch multiple exposure fields together or adopt multi-chiplet designs, two approaches that have their own other challenges, such as tool productivity and power consumption. To circumvent the 6×6-inch photomask limitations, TSMC is working with ASML to set the stage for 6×12-inch photomasks.

Changing the size of photomasks is not a trivial endeavor as it requires changing everything from EDA software to tools that produce and write masks as well as systems that handle them, which essentially means that the entire industry must work on this change. ASML seems to be optimistic about the transition as it is supported not only by Intel and TSMC, but also by Samsung.

"We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips," said Christophe Fouquet, president & CEO, ASML. "We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative."

Perhaps the biggest intrigue about TSMC's usage of High-NA EUV lithography is which process technology will be the first to use the new systems. Based on what we know about TSMC's roadmap, A10 or A11 (1/1.1nm-class) seems to be by far the strongest candidates to use High-NA EUV scanners for the most critical layers. TSMC's latest strategy separates its roadmap into annual client-oriented nodes (N2, N2P, N2X, A14, A13) and roughly biennial high-performance nodes (A16 in 2027, then A12 in 2029). The company has already confirmed that A12 and A13, due in 2029, will continue to rely on conventional EUV lithography.

Since A13 is an optical shrink of A14 that increases transistor density by only 6%, with performance and power improvements yet to be disclosed, its successor in 2030 will likely have to deliver considerably more substantial gains. It is therefore reasonable to expect A13’s successor — whether it is called A11 or A10 — to adopt more advanced lithography and/or TSMC's 3^rd Generation nanosheet GAA transistors to deliver significantly higher transistor density as well as meaningful performance and power improvements over its predecessor. Yet, we are of course speculating.

NEC was one of the first developers of quantum computers back in the 1990s, but it is now among the first companies that originally researched quantum computing technologies to quit development of quantum computing hardware, according to a Diamond Online report. However, the company will continue to investigate practical applications for quantum computers.

NEC has been involved in superconducting quantum computing research since the technology's earliest days. In 1999, NEC researchers demonstrated the world's first superconducting solid-state qubit, which became a foundation of superconducting quantum computing. Variations of this technology are now being used by Google and IBM to build their quantum computers. However, it turns out that the Japanese technology giant quietly ended development of physical quantum computing machines in March 2026, and many of its researchers subsequently moved to rival Fujitsu.

Despite its historical role, NEC has apparently concluded that developing commercial quantum computing hardware will take too long to generate adequate returns. As a result, the company quietly discontinued development of quantum computing machines at the end of March, according to Diamond. A number of researchers involved with the program — reportedly including a key research leader — have since moved to Fujitsu, which continues to invest heavily in superconducting quantum computing hardware.

Meanwhile, NEC does not formally characterize the move as a withdrawal from quantum computing. In response to Diamond, the company declined to comment on whether it had exited quantum computer development and said that it continues to evaluate practical applications and industrialization of quantum technologies as well as conduct proof-of-concept projects with customers. Therefore, the move appears to represent an exit from development of actual quantum computers rather than from quantum technology altogether. NEC can continue working on quantum applications, software, algorithms, and customer projects without assuming the cost and risks associated with designing and building quantum processors and complete quantum computing systems.

For Fujitsu, the arrival of experienced NEC researchers could strengthen an already advanced superconducting quantum computing operation. Last year Fujitsu and Riken launched a 256-qubit superconducting quantum computer and have been working toward a machine with more than 1,000 qubits in 2026. In addition, Fujitsu has outlined plans to develop systems exceeding 10,000 superconducting qubits by fiscal 2030.

NEC's withdrawal is particularly notable because virtually none of the major corporate laboratories that pioneered quantum computing in the 1990s and remain intact today have completely abandoned quantum-computer hardware. IBM, the other major corporate participant in some of the earliest experimental quantum computers, has instead become one of the industry’s largest developers of quantum computing systems.

NEC is no stranger to leaving businesses that have significant prospects ahead but require massive capital investments immediately. In 1990, NEC ranked No. 1 globally in semiconductor sales, ahead of Toshiba, Hitachi, Motorola, Intel, and Fujitsu. Intel subsequently overtook NEC during the 1990s as the PC microprocessor market exploded, but in 1990, NEC was significantly ahead. So, NEC's 1999 superconducting-qubit breakthrough did not come out of nowhere, but from a company with a huge semiconductor R&D organization and deep expertise in solid-state devices. By then, NEC was no longer the No. 1 semiconductor supplier, but it remained one of the world's major semiconductor companies.

The demise of NEC's semiconductor business was not sudden. NEC dismantled its semiconductor business in stages over roughly a decade. NEC effectively gave up doing DRAM alone in 1999, when it spun off its DRAM operations into NEC-Hitachi Memory, which was named Elpida. In November 2002, NEC spun its remaining semiconductor operation — MCUs, system LSIs/SoCs and other devices — into a separate company called NEC Electronics and later renamed Renesas Electronics.

Now, NEC is reportedly stepping away from quantum computer hardware as its commercialization remains distant, but development costs continue to mount. Furthermore, given NEC's current business focus — IT services, enterprise systems, aerospace and defense, telecom infrastructure, and AI and security — quantum computers are not exactly a natural fit.

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.

One million High-NA wafers

Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.

Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.

Sticking to stitching

Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.

Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.

6×12 mask effort progressing

To avoid using stitching, the industry — led by Intel — plans to shift to larger 6×12 masks, which will enable a 26×33 mm full field in one exposure. While this looks easy on paper, make the mask twice as long, changing the mask represents an enormous ecosystem change.

Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.

It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.