© Nick Rohlman/The Gazette, via Associated Press
Leading chipmakers Samsung Electronics and Taiwan Semiconductor Manufacturing Co. announced plans to adopt ASML’s latest chipmaking machines in the next several years—and they also joined Intel in agreeing to a crucial technology change that could boost chip production on the new machines by 40 percent.
This signifies the semiconductor industry’s broader embrace of high NA EUV photolithography technology that can cost up to $400 million per machine and is only provided by the Dutch technology company ASML, Bloomberg reports. The technology would allow chip designers to implement even smaller features in potentially more powerful and efficient next-generation chips produced for AI data centers and consumer electronics such as smartphones, tablets, and laptops.
ASML’s EUV (extreme ultraviolet) lithography machines enable chipmakers to use powerful laser light to imprint patterns in silicon wafers, layer by layer, and gradually form the computer circuitry that makes silicon chips work. Compared to older deep ultraviolet lithography, EUV technology harnesses a more powerful source of light with a shorter wavelength to create even smaller features on silicon wafers.
© Michel de Heer | ASML
Leading chipmakers Samsung Electronics and Taiwan Semiconductor Manufacturing Co. announced plans to adopt ASML’s latest chipmaking machines in the next several years—and they also joined Intel in agreeing to a crucial technology change that could boost chip production on the new machines by 40 percent.
This signifies the semiconductor industry’s broader embrace of high NA EUV photolithography technology that can cost up to $400 million per machine and is only provided by the Dutch technology company ASML, Bloomberg reports. The technology would allow chip designers to implement even smaller features in potentially more powerful and efficient next-generation chips produced for AI data centers and consumer electronics such as smartphones, tablets, and laptops.
ASML’s EUV (extreme ultraviolet) lithography machines enable chipmakers to use powerful laser light to imprint patterns in silicon wafers, layer by layer, and gradually form the computer circuitry that makes silicon chips work. Compared to older deep ultraviolet lithography, EUV technology harnesses a more powerful source of light with a shorter wavelength to create even smaller features on silicon wafers.
© Michel de Heer | ASML
For years, TSMC has tried to avoid making public comments about its plans to use EUV lithography with a 0.55 numerical aperture optics, or High-NA EUV, because the company's developers had a good idea how to keep advancing process technologies without using $400 million scanners. However, TSMC cannot rely on Low-NA EUV systems forever, so this week the company announced plans to use High-NA EUV starting from 2030.
TSMC did not formally reveal which fabrication technology will be the first to adopt High-NA EUV, though the year 2030 points to a few candidates. What TSMC did say is that it expects the number of layers processed using High-NA EUV to eventually increase as its fabrication technologies become more complex, driven by increasing complexity of transistor architectures, which is probably an implication for more sophisticated implementations of gate-all-around (GAA) transistors as well as complementary field-effect transistors (CFETs) later on.
TSMC plans to start using High-NA EUV lithography tools for high-volume manufacturing in 2030 using conventional 6×6-inch photomasks. The company then plans to build a pilot line that uses 6×12-inch photomasks in 2031 with the goal of bringing 6×12-inch High-NA lithography systems into advanced node production by 2033.
High-NA EUV lithography tools can achieve an 8nm single-exposure resolution, as opposed to a 13nm single-exposure resolution offered by today's Low-NA EUV litho systems. However, when used with conventional 6×6-inch photomasks, High-NA EUV scanners have only half the exposure field of their Low-NA counterparts, which creates challenges for manufacturing very large dies. As a result, chipmakers building massive AI accelerators must either stitch multiple exposure fields together or adopt multi-chiplet designs, two approaches that have their own other challenges, such as tool productivity and power consumption. To circumvent the 6×6-inch photomask limitations, TSMC is working with ASML to set the stage for 6×12-inch photomasks.
Changing the size of photomasks is not a trivial endeavor as it requires changing everything from EDA software to tools that produce and write masks as well as systems that handle them, which essentially means that the entire industry must work on this change. ASML seems to be optimistic about the transition as it is supported not only by Intel and TSMC, but also by Samsung.
"We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips," said Christophe Fouquet, president & CEO, ASML. "We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative."
Perhaps the biggest intrigue about TSMC's usage of High-NA EUV lithography is which process technology will be the first to use the new systems. Based on what we know about TSMC's roadmap, A10 or A11 (1/1.1nm-class) seems to be by far the strongest candidates to use High-NA EUV scanners for the most critical layers. TSMC's latest strategy separates its roadmap into annual client-oriented nodes (N2, N2P, N2X, A14, A13) and roughly biennial high-performance nodes (A16 in 2027, then A12 in 2029). The company has already confirmed that A12 and A13, due in 2029, will continue to rely on conventional EUV lithography.
Since A13 is an optical shrink of A14 that increases transistor density by only 6%, with performance and power improvements yet to be disclosed, its successor in 2030 will likely have to deliver considerably more substantial gains. It is therefore reasonable to expect A13’s successor — whether it is called A11 or A10 — to adopt more advanced lithography and/or TSMC's 3rd Generation nanosheet GAA transistors to deliver significantly higher transistor density as well as meaningful performance and power improvements over its predecessor. Yet, we are of course speculating.
A 52-year-old Belgian-Chinese man has been arrested on suspicion of espionage for allegedly transferring specialized semiconductor intellectual property and trade secrets from Belgian chipmaker BelGaN, where he worked, to China. According to an AP News report citing details released by Belgium's federal prosecutor’s office on September 7, the Beijing-born Belgian resident was taken into custody on May 10 at a Brussels airport while attempting to board a flight to China.
The suspect — identified by Belgian media only as H.L. — previously held a senior research position at the now-defunct BelGaN, which specialized in gallium nitride (GaN) semiconductors. Investigators suspect he was concurrently leading a Chinese chip firm, GanKool, which was developing the exact same specialized gallium nitride chip technology as BelGaN. The company was established only a few months after H.L. joined BelGaN and was financed by a Chinese investment fund. The suspect now faces charges of industrial espionage, membership in a criminal organization, misuse of company assets, and unlawful disclosure of business secrets.
The espionage allegations emerged from an investigation into BelGaN's collapse. When the company collapsed into bankruptcy in the summer of 2024, Belgian authorities launched a routine financial probe into the failure. Investigators eventually uncovered highly unusual corporate activity. Instead of trying to keep BelGaN financially viable, the managers and the researcher may have actively tried to make the Belgian company “disappear” after transferring its proprietary knowledge. This led to further investigations that revealed GanKool’s existence and its connections to BelGaN.
In addition to the researcher’s role, the investigators also found evidence linking BelGaN's last CEO, a Chinese national, to the same Chinese rival. The prosecutors have said a second suspect remains at large, with Belgian media speculating that the CEO is the suspect.
The incident highlights the increasingly intense competition over technology and intellectual property in the semiconductor industry, particularly as China pushes to reduce its reliance on foreign chip technology while the U.S. continues to restrict its access to advanced processors and semiconductor manufacturing equipment. Just last month, South Korean court documents accused Chinese memory maker CXMT of using a detailed “Project Hefei” roadmap to obtain Samsung's proprietary DRAM technology, including a 620-step process recipe. A former Samsung engineer has already been sentenced to seven years in prison over the scheme.
Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.
One million High-NA wafers
Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.
Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.
Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.
Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.
To avoid using stitching, the industry — led by Intel — plans to shift to larger 6×12 masks, which will enable a 26×33 mm full field in one exposure. While this looks easy on paper, make the mask twice as long, changing the mask represents an enormous ecosystem change.
Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.
It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.
Machine vision is becoming a practical part of Apple’s U.S. factory training strategy, giving smaller manufacturers access to techniques that help production systems inspect what they make. The recent opening of the Houston manufacturing training center extends that effort into a working electronics production campus, while courses developed with Michigan State University introduce businesses to image analysis, machine learning, and automated quality checks.
For a manufacturer, the attraction can be straightforward: finding a missing component before a product leaves the line, identifying a surface defect before more material is added, or recognizing an assembly error while it can still be corrected cheaply.
These are manageable problems with measurable costs. They also offer an accessible starting point for businesses interested in AI but unsure where it belongs inside their operations.
The Apple Manufacturing Academy’s current course catalog includes Machine Learning with Vision, a course introducing machine learning and deep learning through practical activities using Apple devices. It sits alongside instruction in automation, quality fundamentals, manufacturing data, maintenance, and process improvement.
That placement gives the subject useful context. A camera can produce an image, but a factory needs a decision: accept the part, flag it for review, check its position, or investigate a process that may be drifting out of tolerance.
Machine vision connects image capture to those operational decisions. Some applications use established rules to measure dimensions or identify patterns. Others use machine learning to recognize acceptable variations and defects that are difficult to describe through fixed rules.
The academy’s public description confirms introductory activities with Apple devices. It does not identify a particular iPhone, Mac configuration, software framework, or industrial camera package that every participant must use.
For smaller businesses, the educational value is learning how to define an inspection problem before purchasing equipment. A company that understands what it needs to detect can have a much more productive conversation with an automation supplier.
Apple opened its 20,000-square-foot Advanced Manufacturing Center on August 13. According to the Houston opening announcement, the free program offers small and medium-sized businesses instruction in advanced manufacturing, interactive labs, and experience with representative production equipment.
The first cohort worked with machine learning for quality control and advanced automation. Participants also explored production challenges, used a holographic table, and assembled and laser etched a product.
The location adds context: the center occupies the same Houston facility that builds advanced AI servers and is scheduled to begin Mac mini manufacturing this year. Its teaching program includes final assembly principles and design considerations for printed circuit board assembly.
Houston is the company’s second U.S. manufacturing learning site, following the Detroit academy established with Michigan State University in August 2025. By the Houston opening, Apple said the academy had helped nearly 1,000 workers, students, and entrepreneurs.
That figure measures people reached through the program. It should not be interpreted as 1,000 factories already operating AI inspection systems.
Imagine a small business assembling control panels. Each panel needs the same set of connectors, positioned correctly before the enclosure closes. A machine vision station could check for a missing connector while the assembly remains accessible.
The value comes from catching that error at the right moment. Discovering it after packaging creates extra handling and rework. Discovering it after delivery may involve a return, a service visit, and an unhappy customer.
A useful pilot would therefore begin with that single inspection point. The business could compare the existing process with the assisted one, recording missed defects, unnecessary rechecks, inspection time, and the cost of correcting mistakes.
The camera is only part of the exercise. Workers must agree on what constitutes a defect, collect representative examples, and decide what happens when the result is uncertain.
Those decisions draw heavily on experience already present on the factory floor. An operator may know that an unusual mark is harmless, while a barely visible change in alignment predicts a later assembly problem. Turning that knowledge into consistent inspection criteria is valuable work in its own right.
These are examples of how manufacturers could apply the training, rather than projects Apple has announced for individual participants.
A demonstration can look impressive when every part arrives clean, centered, and evenly lit. Production introduces variation: different surface finishes, reflections, changing positions, and batches that look slightly different while remaining within specification.
The inspection system must distinguish those acceptable differences from actual failures. Otherwise, it can reject good products or allow defective ones to continue.
Industrial vision supplier Cognex’s deployment guidance recommends validating systems across product models, defect types, and manufacturing lines. It also describes an approach in which automated inspection handles preliminary checks while experienced inspectors review borderline cases.
For a business learning machine vision, that offers a realistic way to introduce the technology. Employees can compare its decisions with their own, investigate disagreements, and determine whether the results justify extending its role.
An inspection system also needs an owner after installation. Someone must understand when a product change requires new examples, when equipment needs attention, and when performance has slipped. Training that responsibility into the workforce helps prevent an initially successful project from becoming an unreliable fixture.
The academy’s reach extends beyond companies producing consumer electronics. In its May update on participating manufacturers, Apple highlighted Block Imaging, a Michigan business that services and refurbishes medical imaging equipment.
The company hosted visitors during the academy’s Spring Forum and described applying techniques learned from Apple engineers and Michigan State experts to its operations. Apple reported that the academy had supported more than 150 American businesses at that point.
The announcement did not identify a particular machine vision deployment at Block Imaging or publish a percentage improvement attributable to visual inspection. It does provide an example of the training reaching businesses whose work differs substantially from building an iPhone.
That wider participation could benefit Apple indirectly. More capable domestic manufacturers can support equipment maintenance, tooling, components, and specialized production services. Participation itself does not establish a supplier relationship, but the skills can be used across customers and industries.
The academy’s participation information says eligible small and medium-sized U.S. manufacturers can take courses free of charge. Online learning includes on-demand materials and interactive modules, while in-person sessions add workshops and more personalized instruction.
Digital badges are available for different topics, and completed course materials remain accessible for review. That gives a business room to train an employee around existing production commitments and return to the material when an actual project begins.
Free instruction does not remove the eventual cost of cameras, lighting, integration, maintenance, or employee time. It can help a manufacturer understand those costs before committing to a system.
The first proposal brought back to the factory might be modest: inspect one recurring defect at one station and record the results for several weeks. A supervisor can then weigh the time saved against the extra reviews, maintenance, and mistakes. That is the kind of evidence a business owner can use when deciding whether to install a second station.
The post Machine Vision Joins Apple’s U.S. Factory Training Push appeared first on AppleMagazine.
© Jason Gulley for The New York Times
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