American startup PsiQuantum has begun construction on a facility in Moreton Bay, Australia, where it plans to build and deploy what it calls the world’s first utility-scale, fault-tolerant quantum computer.

The California-based quantum computing company broke ground on the site alongside representatives from the Australian government, the Queensland government, and local officials. The project is expected to become a key part of Australia’s push to establish itself as a hub for advanced computing technologies.

The facility will be developed in multiple phases and will house the infrastructure needed to support PsiQuantum’s photonic quantum computing architecture. One of the first major components arriving at the site will be a large cryogenic plant designed to cool the quantum system.

PsiQuantum said the cryoplant, being built by Linde Engineering, is expected to be delivered in the second half of 2027. The company ordered the system in late 2024 and described it as one of the largest cryogenic cooling plants ever built for a quantum computing application.

Race toward utility

The cooling system will be followed by cryogenic cabinets that will contain photonic quantum chips. These cabinets will be connected using conventional optical fiber, forming the foundation of the company’s planned utility-scale machine.

Unlike many quantum computing efforts that remain focused on laboratory-scale systems, PsiQuantum is pursuing a photonics-based approach designed to scale using existing semiconductor manufacturing processes and optical networking technologies.

“Building a quantum computer that solves real world problems is one of the great engineering challenges of our time. For decades, quantum computing has held the promise of transforming what humanity can achieve through computation, and today in Australia we are beginning to turn that promise into reality,” said Victor Peng, Chief Executive Officer of PsiQuantum.

The company believes fault-tolerant quantum computers could eventually tackle problems beyond the reach of conventional computing systems. Potential applications include drug discovery, materials development, energy research, logistics, manufacturing, agriculture, and financial modeling.

PsiQuantum also sees quantum computing as a complement to emerging computational technologies rather than a replacement. The company said future industrial computing systems are likely to combine quantum and classical technologies to accelerate scientific discovery and solve increasingly complex problems.

Building local capability

The Moreton Bay facility is also expected to support workforce development in Australia’s growing quantum technology sector. The site sits within the Moreton Bay Central Innovation Precinct, close to a TAFE Centre of Excellence and the University of the Sunshine Coast’s Moreton Bay campus.

According to the company, the project will create jobs in engineering, technical operations, advanced manufacturing, research, and professional services. The location is intended to help students, technicians, apprentices, and engineers move directly into careers linked to quantum technologies.

“Australia has been part of this journey from the very beginning,” said Prof. Jeremy O’Brien, Co-Founder and Executive Chair of PsiQuantum.

The groundbreaking follows the opening of PsiQuantum’s Test and Validation Lab at Griffith University in Brisbane in May 2026. The laboratory houses cryogenic equipment used to test photonic quantum chips and supporting systems that will eventually be deployed at the Moreton Bay site.

If completed as planned, the facility will become one of the world’s most ambitious efforts to build a fault-tolerant quantum computer at industrial scale.

The U.S. Department of Defense (DoD) has awarded Parallel Works, an Illinois-based software company spun out of Argonne National Laboratory, a contract to provide a unified platform that connects military supercomputing centers with secure commercial cloud infrastructure.

The contract, granted under the department’s High Performance Computing Modernization Program (HPCMP), will allow scientists, engineers, and acquisition professionals across the DoD to access both on-premises and cloud-based computing resources through a single interface. The goal is to speed up the development and deployment of high-performance computing (HPC) and artificial intelligence (AI) workloads used for defense research and operations.

Parallel Works said its ACTIVATE High Security Platform (HSP) will act as the control plane linking Defense Supercomputing Resource Centers (DSRCs) with commercial cloud services. The platform is designed to let users move workloads across environments while maintaining security requirements for sensitive data.

The company said researchers will be able to test and deploy workloads on emerging cloud infrastructure before those capabilities are integrated into the DoD’s supercomputing centers.

Connecting defense computing

The platform has been approved at Impact Level 5 (IL5), one of the highest security classifications for non-classified DoD cloud environments. According to the company, it is among a small number of software platforms approved to handle export-controlled workloads, including International Traffic in Arms Regulations (ITAR) and Controlled Unclassified Information (CUI).

The system is intended to address growing demand for computing power driven by AI development, simulation workloads, and digital modernization programs across the military.

“AI-driven warfare and the ramp to digital modernization are demanding far more model-sharing options than legacy infrastructure can provide,” said Keith Obenschain, Chief Technology Officer at HPCMP.

The platform offers on-demand access to cloud compute resources, allowing users to avoid traditional queue delays associated with shared supercomputing systems. It also enables organizations to expand computing capacity by distributing workloads across multiple environments and cloud providers.

Parallel Works said users will have access to cloud infrastructure from providers including Amazon Web Services, Microsoft Azure, Google Cloud, and Oracle Cloud.

Accelerating mission deployment

As part of the contract rollout, the Naval Research Laboratory has already implemented the platform to support weather forecasting workloads.

According to the company, the system automates forecasting workflows while securely coordinating computing resources across defense and cloud environments. The approach is intended to improve reliability, speed up processing, and help redistribute workloads when demand spikes.

“The HPCMP contract allows our platform to support a broad range of mission-critical HPC and AI workloads across the DOD teams,” said Matthew Shaxted, CEO of Parallel Works.

The company said the environment can also serve as a secure testing ground for AI development tools and next-generation cloud architectures before they are adopted within the DoD’s existing supercomputing infrastructure.

The contract reflects a broader push by the U.S. military to combine traditional supercomputing resources with commercial cloud services as AI models and data-intensive applications continue to increase computing requirements across defense operations.

KAIST researchers have developed a simulation-based method to predict how small future transistors can become before quantum effects begin to interfere with their operation, a breakthrough that could help engineers design next-generation semiconductor chips more efficiently.

The team used atom-level quantum mechanical calculations to identify the scaling limits of transistors, the tiny switches that control the flow of electricity in electronic devices. The findings could help chipmakers continue shrinking transistors beyond current technology nodes while reducing costly trial-and-error during development.

As the semiconductor industry enters the so-called 2 nm era, the physical dimensions of transistors remain significantly larger than 2 nanometers. One of the biggest obstacles to further miniaturization is quantum tunneling, a phenomenon in which electrons leak through barriers that would normally block them, making it difficult to control current flow.

Understanding where that limit lies has been challenging because it is nearly impossible to directly measure the atomic-scale interactions occurring where metal contacts connect to semiconductor channels.

Chasing atomic limits

To overcome that challenge, the KAIST team relied on first-principles calculations, a computational approach that predicts material behavior using the laws of physics rather than experimental data.

Building on a previously developed framework known as multi-space constrained-search density functional theory (MS-DFT), the researchers conducted virtual transfer length method experiments, a standard technique used to measure contact resistance between metal electrodes and semiconductor materials.

The simulations allowed the team to examine how electrons move across metal-semiconductor interfaces and determine the critical tunneling length, the point at which electron leakage begins to affect transistor performance.

The researchers applied the method to monolayer molybdenum disulfide (MoS2), a two-dimensional semiconductor considered a promising candidate for future transistor channels because it can be manufactured at atomic-layer thickness.

Their analysis showed that electron penetration into the channel varies depending on the choice of metal electrode and the atomic structure of the contact interface. As a result, the minimum achievable transistor size is not fixed but depends on material selection and device design.

Beyond today’s nodes

According to the study, the critical tunneling length changes based on the work function of the metal and the geometry of the contact structure. This means engineers can potentially tune transistor scaling limits by selecting different materials and interface configurations.

Among the combinations studied, the team found that electron leakage could be suppressed at dimensions below 4 nanometers, suggesting future transistors may be scaled even further than current technologies allow.

The researchers also proposed a design strategy that combines two-dimensional semiconductors with different properties to reduce power consumption in future chips.

“This study is significant because it presents a new physical criterion for defining how small next-generation transistors can become,” said Professor Yong-Hoon Kim.

“By computationally analyzing quantum mechanical phenomena in the sub-10 nm regime, which are difficult to probe experimentally, we have opened a path toward utilizing these findings in next-generation transistor design.”

The team believes the approach could provide chip designers with a platform for predicting transistor performance and scaling limits before fabrication begins, potentially shortening development cycles for future AI and high-performance computing chips.

The study was published in the journal npj Computational Materials.