Gaming continues to improve on Windows 11 PCs powered by Snapdragon X chips. A recent Adreno GPU driver improves stability and quality for several titles, though the exact changes you'll see depend on if your system has a Snapdragon X chip or a Snapdragon X2 chip.
Well-known titles including Halo Infinite and Black Myth: Wukong are among the games that will benefit from the driver update for those with Snapdragon X2 processors. Avowed, Borderlands 4, and Dishonored 2 are among the library of games that will improve when running a Snapdragon X chip.
Windows 11 PCs powered by Snapdragon processors have come a long way. A massive library of apps now run natively on Windows 11 on Arm and emulation has improved to fill remaining gaps.
While there are pieces of enterprise and legacy software that do not work with Windows 11 on Arm, the biggest remaining gap is gaming.
Easy Anti-Cheat is now supported, as is Logitech G HUB. Many games now perform better on Snapdragon X systems, but I think it's safe to call it a work in progress.
There are two change logs to go through, one for Snapdragon X and one for Snapdragon X2, both of which were shared on Reddit by user "lexcyn":
Snapdragon X Series Platforms: Game Stability/Quality Improvements
Avowed
Borderlands 4
Dishonored 2
Dishonored: Death of the Outsider
DREDGE
Nobody Wants to Die
RoboCop: Rogue City - Unfinished Business
Seven Deadly Sins: Origin
Split Fiction
Squad
Snapdragon X2 Series Platforms: Game Stability/Quality Improvements
007 First Light
Black Myth: Wukong
Borderlands 3
Dishonored 2
Dishonored: Death of the Outsider
F1 2022
Granblue Fantasy: Relink
Hades 1
Halo Infinite
Hollow Knight
It Takes Two
Lies of P
Seven Deadly Sins: Origin
Split Fiction
Star Wars Outlaws
Yakuza Kiwami 3
Qualcomm and Microsoft continue to work on the gaming experience on Snapdragon X systems. A recent update to Snapdragon Control Panel redesigned game library navigation and improved the software experience.
The Snapdragon X2 Elite Extreme and other Snapdragon X2 chips are more powerful, allowing them to better handle modern games.
When announcing those chips, Qualcomm did not mention gaming in its press release, but it's clear that the company has plans to power gaming PCs with its Snapdragon X processors. ASUS took a different approach and listed the Zenbook A16, highlighting its gaming capabilities.
As more games are optimized and supported, gaming on Windows 11 on Arm will trend upward.
Join us on Reddit at r/WindowsCentral to share your insights and discuss our latest news, reviews, and more.
Apple’s layoffs across Siri, AI, Vision Pro, and software teams sparks discussions about shifting priorities, institutional knowledge, and the future of spatial computing. The MacVoices Live! panel also debates the privacy implications of ChatGPT remembering Mac activity, the advantages of on-device AI, and Walmart’s long-overdue decision to embrace Apple Pay and NFC payments. The panel […]
Apple’s new Mac mini and Mac Studio spark a discussion of the M6 and M5 Ultra chips and how they measure up in performance and upgrade decisions. The panel weighs Mac Studio trade-ins, Mac mini value, on-device AI and large language models, and Apple’s increasingly powerful silicon. They also examine the move to 2-nanometer technology and debate Apple’s redesigned keyboards and glyph-only modifier keys.
M6 is built using cutting-edge 2 nm process technology, packing greater transistor density into a smaller die for a major leap in performance and power efficiency. M6 also introduces a Dual 16-core Neural Engine, providing up to 2x the peak compute over previous generations to make on-device AI workflows run even faster. System frameworks can automatically utilize both engines simultaneously, enabling applications to see faster model execution.
M6 has a brand-new 12-core CPU complex — two more cores than M5 — that consists of 2 super cores, 4 performance cores, and 6 efficiency cores. It delivers the world’s fastest single-threaded performance and up to 1.2x faster multithreaded performance as compared to M5, and up to 2.4x faster than M1.
[…]
M5 Ultra uses UltraFusion to connect two dual-die M5 Max chips to form the quad-die architecture — a first for Apple silicon. UltraFusion increases the inter-die bandwidth to over 4.4TB/s and the connection density by over 6x. Together, these ultra-low-latency, high-bandwidth interconnects allow the four dies to behave as a single unified processor. M5 Ultra also features a large up-to-36-core CPU consisting of 12 super cores and 24 performance cores, delivering up to 1.25x higher single-threaded performance and up to 1.3x higher multithreaded performance than M3 Ultra.
M5 Ultra features a next-generation GPU with up to 80 cores, incorporating a Neural Accelerator in each core to offer up to 4.5x the peak GPU compute for AI compared to M3 Ultra and over 6x more than M1 Ultra.
It was not long ago all the illustrations in an M chip press release were graphs showing it flouncing the competition. Now it’s just random screenshots of desktops. Skimming this I didn’t see a single claim of performance advantages over competitors. The massive thing Apple still needs to solve is making sure customers don’t miss being able to plug the latest greatest GPU into their tower, they should not be resting on their laurels.
The most significant architectural change is in the CPU. The M5 splits its ten cores into performance and efficiency groups, which is an arrangement Apple silicon has used since the M1. The M6 adds a third tier called “super cores,” which handle single-threaded workloads and which Apple says give the chip the world’s fastest single-threaded performance.
[…]
Apple did not publish real-world benchmarks comparing the M6 to the M5 directly, instead framing its Mac mini figures against the M4 and M1 models[…]
[…]
Bloomberg’s Mark Gurmanreported in July that Apple has no plans to release “M6 Pro,” “M6 Max,” or “M6 Ultra” chips, having decided to accelerate development of the AI-optimized M7 generation.
As with previous Ultra generations, the M5 Ultra combines two M5 Max chips, but since they’re dual-die chips, the result is Apple silicon’s first quad-die architecture. (The M3 Ultra connected two single-die M3 Max chips.) There’s no practical benefit to users in a quad-die architecture, but it’s a huge win for Apple. The larger the die, the more difficult and expensive it is to manufacture because a defect can ruin the entire die. Dividing the design into smaller dies can substantially improve manufacturing yield and reduce costs.
[…]
The M5 Ultra dispenses with efficiency cores entirely, devoting all CPU resources to super and performance cores.
If this single Geekbench 7 result is accurate, the M6 chip has up to around 12% faster single-core CPU performance and up to around 27% faster multi-core CPU performance compared to the M5 chip.
Unsurprisingly, the M5 Ultra is Apple’s fastest chip ever. If this Geekbench result is accurate, it has up to around 30% faster single-core CPU performance and up to around 35% faster multi-core performance compared to the M3 Ultra.
It feels like every week the component crisis worsens, driving the prices of hardware for even mid-level PC gaming to insane prices that only a few could afford without draining their savings.
Fortunately, price discounts are still a thing, giving us PC players brief respites from this RAMpocalypse. One such deal is this 26% discount for AMD Ryzen 7 7800XD, reducing the price of one of our favorite gaming CPUs from $449.99 to $333.99 on Amazon.
"Dominate any game at any level, the Ryzen 7 7800X3D offers ultimate performance with 8 cores, 16 threads, and up to 5.0GHz boost clock backed up with 96MB L3 cache." — Ben Wilson & Harish Jonnalagadda, Senior Editors
The AMD Ryzen 7 7800X3D in hand. (Image credit: Windows Central (Ben Wilson) | AMD)
The AMD Ryzen 7800X3D may be three years old, but it's still packing plenty of processing power to help your PC run games with extremely high performance that will make them feel so much smoother and more responsive to play with.
How high, you may ask? Well, my colleague, Ben Wilson, confirmed in his 4.5-star review of the AMD Ryzen 7 7800X3D that its 3D V-Cache makes an obvious difference to games, even if it doesn't thrill in productivity.
Shadow of the Tomb Raider benchmark.Ben Wilson | Windows CentralCyberpunk 2077 in-game at 200 FPS+.Ben Wilson | Windows CentralCyberpunk 2077 benchmark.Ben Wilson | Windows Central
You can boost the AMD Ryzen 7 7800X3D's performance further by overclocking it using the Precision Boost feature with the Ryzen Master app. This is all done while the AMD Ryzen 7 7800X3D's power management system keeps it stable and cool.
However, don't expect to use this CPU for grinding through productivity tasks in a speedy manner, as its performance rates in this regard are somewhat lacking compared to Intel's (often more expensive) offerings.
Additionally, the AMD Ryzen 7 7800X3D isn't compatible with DDR4 RAM, so folks running PC rigs with older RAM may need to upgrade (which is easier said than done thanks to this AI-induced RAM crisis sucking all our RAM dry).
The memory crisis is getting worse for Apple, which is struggling to get enough memory chips together for its upcoming iPhone 18 Pro series smartphones. That’s according to tech journalist Tim Culpan.
As he details it, Apple and its assembly partners are still attempting to secure sufficient quantities of memory, and though they’re confident they can meet initial demand once the devices are introduced, they apparently remain concerned that wait times could rapidly extend as retail inventory evaporates.
Apple’s manufacturing process compounds the problem. The A20 processor is packaged with memory using a new TSMC process, meaning processors are reportedly piling up while manufacturers wait for memory chips. You should read Culpan’s report to get the full picture.
What’s the frequency?
You don’t need to read between the lines to see the challenge. Despite demand for TSMC’s new processors, Apple seems to have been able to secure the supply it needs. But when it comes to churning out the final packaged chips memory, supply constraints have created significant obstacles to producing in quantity.
This is bad for Apple, particularly as the challenge doesn’t appear to be confined to iPhones; customers are experiencing delays getting new Macs. “Many new orders are now not arriving until September,” Bloomberg’s Mark Gurman wrote earlier this week.
It isn’t just Apple that will be impacted by the AI-driven memory drought. The scale of Apple’s orders is among the greatest in the industry, and if its product plans are feeling the pain, every other manufacturer will be feeling it as well.
Conscious uncoupling
This is certainly in tune with expectations voiced at the beginning of the year when Ranjit Atwal, senior director analyst at Gartner, warned: “This is the steepest contraction in device shipments witnessed in over a decade. Higher prices will narrow the range of devices available, prompting buyers to hold on to devices for longer, fundamentally altering upgrade cycles.”
Gartner in February predicted a 10.4% decline in global PC shipments and an 8.4% drop in smartphone shipments as a result. The analyst also predicted a 130% surge in combined memory and SSD storage prices by the end of this year, with steep product price increases to follow. Recent data from IDC, Gartner, Counterpoint, and Omdia confirm PC market declines, but only at around 4% (the estimates vary).
Today’s report from Culpan suggests we’ve not yet experienced the full extent of this decline — hinting that while the initial fall reflected price, the next impact will be defined by lack of supply. While this hurts big brands like Apple, smaller entities could be left high and dry.
When the chips are down
It is interesting to reprise Atwal’s warning in February that, “the sub-$500 entry-level PC segment will disappear by 2028,” as this seems to be what’s happening. That’s something long-time Mac users like me find particularly ironic, given it was only this year Apple briefly offered up its superbly priced $499 MacBook Neo. The industry direction we’re seeing now suggests we’ll never see that again, though the success of that device gave Apple a phenomenal 28.7% increase in sales in its just-revealed June quarter.
Despite memory supply challenges, Apple seems to be faring fairly well, with market share increasing across its business. Counterpoint data reveals that Apple has achieved an astonishing 65% share of the premium smartphone market. In part, that’s because as an existing premium brand, Apple was able to better absorb rising memory costs through higher margins and reduced promotions. Realistically, this means we can expect an overall increase in iPhone prices when the new range is announced up to $300 more, Jeff Pu, of GF Securities, recently claimed.
Building the moat
Once again, what’s sustainable but difficult for larger brands such as Apple is existential disaster for smaller players — and it’s only now a matter of time before we see some real blood. That’s particularly true in smart home and device markets, where manufacturers lack the margins to sustain higher memory prices while delivering products customers can afford. A recent Global Electronics Association report tells us 62% of electronics manufacturers are already experiencing constrained availability or extended lead times. It also tells us 82% expect rising prices, including 33% who cite a “significant increase.”
This is already being felt by consumer and business users, as networking equipment is experiencing significant shipping delays. So, while we may find ourselves waiting a month or more for an iPhone, the wait for new routers, external storage devices, and home automation systems could be even longer once available inventories disappear.
This doesn’t appear to be a short-term challenge; a recent Digitimes report warns that vendors have already sold their entire allocation of memory capacity for 2027.
Don’t even get me started on the likely impact on the military and defense markets as high-performance memory, storage, and processor supplies become constrained. Just like declining river levels in Europe, lack of memory threatens severe disruption. With so much turbulence impacting the tech economy, all we need now is for one or more of theinvestor-supported AI companies that have helped create the memory shortages to default on loan payments.
Got to keep the customer satisfied
Eager to protect sales, Apple recently introduced the Apple Upgrade leasing service in the US. This should enable consumers to purchase new devices at prices more sustainable to them over time. Apple isn’t alone in taking such action, which will inevitably extend beyond America.
“OEMs are expanding financing, trade-in and buyback programs to improve affordability,” said Counterpoint’s Harshit Rastogi. “Samsung has also expanded its Galaxy Forever program to several markets to make flagship devices more accessible.”
Such schemes are all well and good, of course. Consumers will embrace them in hopes of a better tomorrow. But the tech industry is not immune to the wider constellation of existential challenges impacting economic environments.
In the end, if Apple, the industry’s biggest buyer of advanced components, is struggling to secure memory, the rest of the electronics sector is likely to face even greater challenges. For consumers, the initial impacts will be longer waits and higher prices. But the longer term consequences could be slower innovation and increased consolidation across the industry.
AMD executives took to the stage at its Advancing AI 2026 event in San Francisco today to detail the company’s next generation of AI infrastructure solutions, from Instinct MI455X AI accelerator GPUs and 6th Gen EPYC “Venice” CPUs, to Pensando networking, ROCm.AI software and its Helios rack-scale platform that ties it all together.
AMD has been working towards rack-scale AI system solutions for years. Its ZT Systems acquisition last year added valuable engineering talent and intellectual property that is now finally bearing the real fruits. Its Helios AI platform is a major platform evolution for AMD, with shipments scheduled to begin in the second half of this year (which is here and now).
The announcements at Advancing AI show how the company has engineered its AI platform solutions for large reasoning models, sustained inference and agentic workflows. These workloads pressure memory capacity, data movement, networking and CPU orchestration. AMD’s approach is to keep as much data close to the compute engines as possible and move it more efficiently throughout the system, but there’s deeper nuance here that’s obvious versus AMD’s chief rival, NVIDIA.
AMD’s MI455X targets the AI memory wall
The Instinct MI455X GPU is the compute engine that fuels the Helios rack, and the first GPU based on AMD’s new CDNA 5 architecture. Built with a modular mix of 2nm and 3nm chiplets, it carries 432GB of HBM4 and 23.3TB/s of peak memory bandwidth.
Compared to AMD’s current MI355X, the MI455X offers 1.5 times the memory capacity, up to 2.9 times the peak memory bandwidth and up to four times the peak matrix performance with MXFP4 and MXFP8 data types, which are lower-precision numerical formats designed to accelerate AI processing while reducing memory demands. With MXFP6 (6-bit floating point), performance is rated at up to twice that of MI355X.
AMD also shared some actual, measured internal results using production silicon. The company claims MI455X delivers 3.8 times higher FP8 decode performance, 3.5 times more measured FP4 compute performance and between 2.5 and 3.5 times more networking bandwidth than MI355X, depending on the transfer path tested. Those figures provide more context than just numerical specifications, though they remain AMD-provided comparisons that will need independent validation.
AMD
The architectural choices behind the numbers are important. Reasoning models and long context windows require sizeable KV caches for maintaining AI attention states, while mixture-of-experts models frequently move large amounts of data across accelerators. MI455X should let more model data, activation states and cache remain local. New dedicated IP in hardware can transfer data while the GPU continues processing, and expanded cache and multicast capabilities are designed to reduce redundant data movement to further improve efficiency.
The aforementioned lower-precision formats can also raise throughput and reduce memory use, but model developers still have to determine where they can be applied without unacceptable accuracy loss.
AMD’s Helios rack takes aim at Vera Rubin
Dave Altavilla
Helios is AMD’s primary rack-scale competitor to NVIDIA’s Vera Rubin platform. Each liquid-cooled rack combines 72 MI455X GPUs, 18 single-socket Venice host CPUs and Pensando networking technologies.
In its most complete, premium configuration, AMD rates Helios for 2.9 exaflops of low-precision AI compute, with 31TB of aggregate HBM4 capacity, 1.7PB/s of memory bandwidth, 260TB/s of bidirectional scale-up bandwidth and 43TB/s of scale-out bandwidth.
These are formidable figures, but they are technical specifications rather than actual application benchmarks. The more consequential development is AMD’s move from collections of eight-GPU servers to a 72-GPU shared-memory domain. Models too large for one node can operate across the rack without treating every exchange as a scale-out networking transaction, which benefits large-model inference as well as training.
AMD uses UALink over Ethernet, or UALoE, for an open standard scale-up fabric. Each MI455X provides 3.6TB/s of bidirectional scale-up bandwidth, while the complete rack delivers all-to-all connectivity through a single switch layer. AMD also claims six times more scale-out bandwidth per GPU than MI355X when MI455X is configured with three Pensando Vulcano 800 AI NICs.
While open standards give cloud providers more control over suppliers and system design, AMD and its partners now have to prove those components can deliver the predictable performance, reliability and deployment experience customers expect from a tightly controlled, more vertically integrated platform.
Finally, AMD designed Helios with automatic rerouting around failed links, virtual rack partitions, tray-level serviceability and rack-wide power, cooling and health monitoring. Major hyperscalers and potentially large-scale enterprise customers will likely key in on these capabilities, which can affect the availability, total cost and consistency of the AI services they consume.
Kind of like cowbell, AMD Venice gives agentic AI more CPU
AMD
AMD’s agentic CPU messaging regarding its upcoming Venice-based EPYC processors is mostly marketing speak, but the underlying requirement is very real. An AI agent can invoke retrieval, databases, security checks, code execution and other tools before a GPU generates a response. Running many agents concurrently increases the amount of conventional compute requirements surrounding the accelerators.
Venice scales to 256 Zen 6 cores with support for 512 threads, 16 memory channels, up to 1GB of L3 cache per socket, along with PCIe 6.0 and CXL 3.1 connectivity. AMD is also offering several Venice configurations for other applications, including general-purpose servers, high-frequency workloads, GPU hosts and high-density CPU sandbox systems used to execute agent tools.
Treating the CPU solely as a GPU host understates its role. Gateways, tokenization, vector search, databases and short-lived code execution stress different mixes of per-core performance, thread count, memory bandwidth and I/O. Specifically, AMD’s internal testing shows Venice significantly outperforming its current EPYC 9965 Turin CPU across five parts of the agentic AI pipeline, including gateway processing, context assembly, vector search, enterprise applications and short-lived tool execution. Individual gains vary by workload, but AMD details the overall generational improvement at up to a 1.7 times lift. As with the MI455X figures though, these comparisons come from AMD and will require independent validation.
Pensando networking and ROCm software advance
Keeping GPUs fed with data and coordinating traffic across racks directly affects utilization and operating costs. In fact, GPU utilization is a pretty sad state of affairs currently for some of the major frontier model providers.
As such, Pensando networking has become central to AMD’s roadmap. Helios can connect each MI455X to as many as three 800Gbps Vulcano AI NICs, while Salina DPUs handle front-end networking and infrastructure services.
On the software side, which is an equally critical component, AMD also introduced ROCm.AI, an AI-assisted development layer due to arrive in August. It includes reusable skills for coding agents, simplified management and Hyperloom, which can profile workloads, tune serving configurations, modify kernels and validate results.
These tools address two persistent AMD challenges: developer efficiency and ease of use, and software tuning. Automated optimization still has to produce repeatable gains without creating hard-to-maintain code, however. And while ROCm has progressed significantly over the last few years, NVIDIA’s CUDA retains an advantage in maturity, tooling and developer familiarity.
AMD now has commitments that give its MI450 generation and Helios considerably more weight. Meta and OpenAI have announced multi-generation agreements composed of up to 6GW of AMD compute capacity, with initial 1GW deployments planned for the second half of 2026.
Oracle plans a 50,000-GPU public cloud cluster beginning in the third quarter, while Microsoft will deploy Helios for Azure AI inference. Finally, just before the AMD event, Anthropic announced a strategic partnership for up to 2 Gigawatts of AMD-fueled AI compute, with its first gigawatt expected online in the first half of 2027.
Commitments of this scale reflect confidence in more than just MI455X performance. These customers are evaluating the complete architecture, including Venice CPUs, Pensando networking, ROCm software, rack integration, serviceability and AMD’s ability to deliver and execute across multiple product generations.
There is some financial alignment behind the agreements as well. AMD issued OpenAI performance-based warrants and committed to investing up to $5 billion in Anthropic. That context matters when evaluating these deals as market validation, but these planned deployments are substantial nonetheless and put Helios on a much stronger foundation as it begins shipping.
AMD expands its robotics and embedded foundation
AMD also expanded its physical AI portfolio, building on credible traction from its Xilinx-derived Kria adaptive system-on-modules and embedded technologies that are already powering robotics, machine vision and industrial automation applications.
The new Ryzen AI Embedded X100 combines up to 16 Zen 5 CPU cores, integrated Radeon graphics, a second-generation NPU and as much as 128GB of unified LPDDR5X memory shared across its compute engines. To me this looks a lot like a repackaging and optimization of the company’s Strix Halo platform, but with specific optimizations for the embedded space. Regardless, AMD is pairing X100 with the Kria AI Robotics Developer Platform, which includes a System Module or SOM, and a new Robotics Partner Network spanning hardware, software and platform providers.
Samples began shipping in June, with full production expected in the fourth quarter. This broader objective is to give developers a path across AMD x86 CPUs, GPUs, NPUs and FPGAs for real-time autonomous systems, rather than requiring them to assemble those hardware engines and software components independently.
Execution for AMD is now the test
AMD has assembled a credible platform for the burgeoning agentic AI market that’s blowing up currently with no signs of stopping. MI455X addresses memory and data movement, Venice handles dense agentic CPU workloads, Pensando networking connects global system resources, and ROCm.AI addresses software complexity. Finally, Helios assembles these components into a true competitive threat for NVIDIA’s latest Vera Rubin platform.
AMD’s open architecture may appeal to customers seeking supplier choice, but openness must also translate into reliable deployments, competitive total cost and software that does not require a significant rip-up. NVIDIA enters this cycle with a stronger ecosystem and far more rack-scale deployment experience. The true test will be how easily and reliably customers can integrate, operate and maintain these AMD solutions at scale.
As it stands, AMD now has major customers and a clearly defined architecture with systems engineering expertise behind it. Delivering Helios on schedule and showing that its performance claims translate into a real production workload throughput advantage and total cost of ownership gains will determine how much the competitive gap narrows. And of course, this is in a market that is clamoring for ever-more compute resources with a seemingly insatiable demand for AI services and capacity. That’s an environment for big iron success. Now AMD just has to deliver optimized, turnkey AI platforms. This is far easier said than done, but time will soon tell as deployments take shape this year.
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In an exclusive conversation with The Deep View ahead of WWDC 2026 in June, Doug Brooks, senior product manager of Apple silicon, discussed how Apple’s long-term investments in neural processing, unified memory, power-efficient computing, and hardware-software integration have positioned its devices for the AI era.
He also explained why Macs have become a favorite platform among AI developers, why Mac minis and Mac Studios are emerging as the preferred AI agent machines, and how Apple sees the future of on-device AI across iPhone, iPad, and Mac.
[…]
“We build a chip knowing exactly what systems it’s going to go into. The chip can influence the system design, and the system design can influence the chip requirements. They’re married together very tightly. I’d actually go a step further and include software in that equation. As we enable new capabilities in the chip, we want to make sure those capabilities are exposed all the way through the software stack so developers can benefit and customers can benefit. Because if those transistors go unused, what’s the point? It’s not about adding something and hoping somebody finds a use for it. We want those capabilities available to solve real problems. I think that’s what allows us to build better systems and ultimately better products.”
It seems like a lot of it is just that developers like macOS.
Hot Macs have their own paradox: open Activity Monitor, select the CPU view, and at the top of the CPU % list will be kernel_task hogging the CPU cores with 100% or more, rather than its usual 4% or so. Kerb any temptation to kill it and hope it goes away, as it has taken control of your Mac to let it cool.
[…]
There are rare occasions when fans blow full on and kernel_task goes wild without any thermal problem. In Intel Macs, resetting the SMC is usually curative, but this could instead be the result of a fault in a thermal sensor, or in the SMC. Hardware diagnostics should tell you more. By far the most common cause of persistent problems is dust and debris in the air ducts, and in the case of some Intel Mac notebooks overheating of the left USB-C ports. For more details, see Apple’s note about kernel_task, which also confirms what I have written here.
[…]
If your Mac is showing early signs of thermal strain and still running, encourage heat loss by immediately[…]
It boggles my mind that the biggest software company in the world, with total control of their hardware/software stack is totally incapable of shipping an OS that doesn’t include one or more daemons who just endlessly waste CPU cycles.
Bonus irony points because dasd’s purpose is supposedly to schedule low priority background processes.
Continuing with the results from file compression, it’s straightforward to calculate the total energy required to compress the test file using the P and E cores:
When compressing using the ten P cores, power used was 51 W for a total of about 8.4 seconds, thus 428 J, or 43 J per core.
When compressing using the four E cores, power used was 255 mW for a total of about 150 seconds, thus 38 J, or 10 J per core.
[…]
In omitting GPU power from Energy Impact, many power- and energy-intensive tasks will appear far less demanding than they really are. This is becoming even more important now Apple silicon chips are being used increasingly to run AI computation locally.
Neither powermetrics nor Activity Monitor provide any estimates of power or energy used by other parts of a Mac, such as memory or the internal SSD, although those can also be important determinants of battery endurance and heat generation.
Nvidia and Microsoft this month touted the reinvention of computers with a new class of “agentic AI PCs” that will “reinvent the way PCs work.”
That’s how Nvidia CEO Jensen Huang described the computers at the recent Computex trade show. At the event, Nvidia introduced its first AI-focused PC chip called N1X, which has an integrated CPU and GPU and will be used in agentic AI PCs.
Nvidia’s new RTX Spark PCs are the first in a major “PC reinvention for 40 years,” Huang said, likening them to AI phones. “You could talk to it, it could look at you. You could ask it to read files… [or] go help you do research.”
Not so fast, say analysts, who argue the computers are mostly repackaged AI PCs that shouldn’t necessarily drive enterprise upgrades.
“Agentic AI PCs is a strange term that should probably be deemphasized,” said Leonard Lee, principal analyst at neXt Curve. “Depending on use case, PCs of the last two generations are ‘agentic AI’-capable.”
Skeptical of the hype, analysts said many current PCs are already capable of running agents, such as those spun up on device by OpenClaw. Those agents don’t need to communicate with AI models in the cloud.
In fact, Lee said, Apple has already shown that Windows isn’t needed to run agentic workloads, with the Mac Mini among the most talked-about device for hosting personal AI agents and OpenClaw.
Analysts said the definition of agentic AI PCs really comes down to the hardware inside, which largely defines their capabilities. Most are really just an evolution of earlier AI PCs, which arrived a few years ago amid similar hype.
AI PCs, specifically CoPilot+ PCs, were originally designed with neural processing units (NPUs) to support the requirements of Windows Recall. “Some argue agentic AI PCs need more GPU compute, but…Qualcomm and Microsoft would counter that agentic AI PCs have been around for a while,” Lee said.
To highlight the capabilities of the RTX Spark PC, a demonstration at Computex showed how an architectural design workflow could be split between the PC and the cloud. (An MCP server managed data exchange to facilitate the cloud-PC workflow.)
Adobe has reengineered Photoshop and Premiere for RTX Spark PCs, allowing the software to communicate with AI agents on PCs and tools to run twice as fast, Huang said.
And at the company’s recent Build conference, Microsoft CEO Satya Nadella demonstrated the new Surface Laptop Ultra AI PC based on the RTX Spark design. He positioned agentic AI PCs as running a new execution layer that can act across files and devices, including generating and executing code.
While AI PCs with agents will be capable, they still lack applications, said Jim McGregor, principal analyst at Tirias Research. “However, PCs — especially the small form factor PCs and workstations — are likely to be the home AI appliance,” he said.
For enterprises, upgrading to RTX Spark PCs at this point could pose problems. That’s because Nvidia’s N1X CPU is based on the Arm processor architecture and could run into compatibility issues with x86 applications designed for Intel and AMD chips.
“Despite Arm processors being available for a while, enterprise penetration stays small, since compatibility with all apps, drivers, and corporate systems is critical and requires extensive testing…, even though Microsoft has done a reasonably good job with Windows 11 on Arm,” said Jack Gold, principal analyst at J. Gold Associates.
Because Microsoft is moving to natively incorporate AI into Windows, those PCs will land in enterprises ultimately, Gold said.
Regardless of hype, it might be a good time for enterprises chasing an agentic AI agenda to upgrade laggard Windows 10 devices, Lee said. “Considering the considerable hype about agentic AI, early adopters will need to upgrade their fleets if they pursue a broad agentic AI agenda for their organizations,” he said.
A groundbreaking advancement in photonic technology promises to redefine the landscape of medical artificial intelligence (AI) diagnostics, as a research consortium led by Professor Han Zhang at Shenzhen University has unveiled a novel all-fiber photonic AI platform utilizing black phosphorus (BP)-based tunable modulators. This innovative approach, which hinges on photon-based computing, surmounts the intrinsic constraints posed by traditional electronic processors, delivering unprecedented energy efficiency and ultrafast performance crucial for real-time clinical decision-making.
The prevailing paradigm in medical AI, deeply reliant on electronic architectures such as GPUs, faces severe limitations related to energy consumption, heat dissipation, and processing latency. These factors collectively impede the integration of AI into time-sensitive diagnostic workflows and exacerbate systemic carbon footprints. Photonic computing, with its reliance on photons rather than electrons, offers dramatically accelerated data transmission speeds and parallelism through wavelength multiplexing, alongside near-zero heat generation. Until now, however, the practical implementation of photonic AI had been hampered by the bulkiness, inefficiency, and fabrication challenges synonymous with conventional optical modulators.
Professor Zhang’s team has ingeniously engineered an atomically thin van der Waals heterostructure by stacking black phosphorus and molybdenum disulfide (MoS2), leveraging the extraordinary optoelectronic properties of these 2D materials. This heterostructure is meticulously integrated onto a microfiber knot resonator (MKR), an ultra-fine looped optical fiber with a diameter narrower than a human hair. This configuration significantly intensifies the interaction between light and material, enabling modulation of the refractive index with minimal applied voltage, which shifts the light’s wavelength to encode computational information with remarkable precision and energy economy.
The fabrication process commences with mechanical exfoliation to obtain pristine BP/MoS2 bilayers, followed by a dry transfer technique to position these heterostructures onto the MKR. The MKR’s torsional geometry enhances evanescent field coupling, ensuring that the optical mode overlaps maximally with the active layered materials. To broaden the modulator’s linear response and suppress nonlinear distortions, the researchers incorporated a Ring-Assisted Mach–Zehnder Interferometer (RAMZI) design. This integration extends the operational voltage range, ensuring fidelity and robustness essential for medical-grade AI computations.
The team transcended single-device innovation by architecting a full all-fiber photonic neural network (PNN). By deploying two RAMZI modulators in tandem with a highly sensitive photoreceiver within a sophisticated time-division multiplexing schema, they realized a closed-loop, coherent computing unit capable of executing neural network operations entirely in the optical domain. This milestone substantiates the transition of photonic neural networks from theoretical constructs to viable, deployable platforms for clinical diagnostics.
Clinical performance validation was conducted in collaboration with esteemed hospitals. The PNN demonstrated expert-level diagnostic accuracy in two stringent medical tasks: detecting retinal detachment from B-scan ultrasound imagery and diagnosing hepatocellular carcinoma (HCC) using multiphase liver computed tomography (CT) scans. Diagnostic accuracy and specificity metrics paralleled those of seasoned radiologists, underscoring the system’s potential for integration into frontline healthcare.
Beyond accuracy, the photonic system showcased transformative efficiency advantages. While a conventional NVIDIA A100 GPU requires approximately 85 milliseconds to process a liver CT study, the photonic platform accomplished the same in a mere 0.8 milliseconds. Additionally, the energy expenditure per operation plummeted to an astonishing 0.608 femtojoules, a staggering 246-fold decrease compared to electronic counterparts consuming 150 femtojoules. This synergy of speed and efficiency paves the way for deploying AI diagnostics in resource-constrained or mobile medical environments like rural clinics and ambulances, dramatically expanding access to critical health services.
The system’s environmental implications cannot be overstated. Conventional AI’s sizable energy footprint contributes appreciably to healthcare’s carbon emissions. The BP/MoS2-based photonic platform fundamentally disrupts this model by combining ultrafast processing with near-negligible thermal dissipation, forging a sustainable pathway for green AI implementations in medicine. This breakthrough aligns with expanding global commitments to environmentally responsible technologies without sacrificing computational power.
Acknowledging the infancy of current implementations, the authors outline avenues for scaling. Presently limited to a single processing layer realized through two modulators, the system’s complexity and image resolution capacity necessitate expansion. A promising strategy involves wavelength-division multiplexing (WDM), exploiting the device’s ∼30 nm bandwidth resonances to channel up to 40 distinct wavelengths. This parallelism would amplify computational density approximately 40-fold while maintaining the existing clock rate, facilitating thousands of multiplications per network layer—an enhancement critical to tackling high-dimensional medical image data.
Device longevity and stability pose additional challenges, given the sensitivity of BP to environmental degradation. While the MoS2 layer affords interim encapsulation, the team plans industrial collaboration to pioneer large-scale protective coatings via atomic layer deposition of Al2O3 and scalable chemical vapor deposition processes. These advancements will bolster device durability, uniformity, and manufacturability, accelerating clinical adoption and commercial viability.
The study also signifies the maturation of fiber-based photonic neural networks into practical diagnostic platforms rather than experimental novelties. Optical fibers’ inherently low transmission loss (<0.2 dB/km), synergized with the modulator’s efficient 0.25 V·cm electro-optic response and expanded linear range, addresses critical bottlenecks impeding prior photonic computing endeavors. Consequently, the technology promises to empower future applications in drug discovery, genomics, and real-time clinical imaging with unmatched energy footprints.
The pioneering work led by Professor Han Zhang not only foregrounds interdisciplinary collaboration across physics, materials science, and biomedicine but also sets a precedent for industry-academia partnerships catalyzing the commercialization of ultrafast photonic devices poised to transform healthcare AI. As research progresses towards integrated multi-layer architectures and industrial encapsulation, the healthcare sector stands on the cusp of embracing a new generation of diagnostic tools that are faster, greener, and broadly accessible.
This heralds a paradigm shift where medical AI transcends the limitations inherent to electronic systems, embracing photon-driven computing as a sustainable, high-performance alternative that aligns with the twin imperatives of clinical excellence and environmental stewardship.
Subject of Research: People
Article Title: Tunable phosphorene modulators – accelerating medical diagnosis with ultra-efficient photonic platforms
News Publication Date: 28-May-2026
References:
Zhang, H., Liu, Y., Wang, H., Zhu, H., et al. (2026). Tunable phosphorene modulators – accelerating medical diagnosis with ultra-efficient photonic platforms. Opto-Electronic Advances. DOI: 10.29026/oea.2026.250332
Image Credits: Professor Han Zhang of Shenzhen University
Keywords: photonic computing, black phosphorus, molybdenum disulfide, van der Waals heterostructure, microfiber knot resonator, electro-optic modulator, photonic neural network, medical imaging AI, energy efficiency, wavelength-division multiplexing, ultrafast diagnostics, sustainable healthcare
In the rapidly evolving realm of artificial intelligence and deep learning, conventional electronic computing architectures are increasingly strained by the demands of large-scale data processing and intricate computational tasks. Optical computing has risen as a compelling alternative, leveraging the inherent physical phenomena of light—such as interference and diffraction—to execute computations fundamentally differently from traditional electronics. By harnessing these optical effects, optical computing systems (OCS) promise unparalleled advantages: notably superior processing speeds, heightened energy efficiency, and a natural aptitude for massive parallelism. These attributes make optical computing especially attractive for intensive applications like image processing, machine learning, and big data analytics, holding transformative potential across these domains.
Yet, despite these promising characteristics, contemporary optical computing platforms grapple with a significant bottleneck rooted in their hardware-centric development workflows. Conventionally, researchers must directly engage with physical OCS hardware to develop, tune, and validate computational tasks. This process entails sequential access to a limited number of costly and often heavily utilized devices. Users must physically occupy the system to load parameters, fine-tune configurations, and iteratively calibrate the hardware—an intrinsically tedious and time-consuming cycle. Each new user or task demands resetting the system state, leading to protracted queues, repetitive adjustments, and redundant calibrations. The resulting workflows impose long hours of equipment occupation and elevated trial-and-error expenses, stifling the possibility for concurrent task development and drastically curtailing research throughput and system agility.
To surmount these entrenched challenges, cutting-edge research has introduced the concept of the Digital Twin Optical Computing System (DT-OCS). This innovative approach establishes a high-fidelity digital replica—a “digital twin”—of the physical OCS that accurately models its input-output behavior under varying configuration parameters. Crucially, the digital twin allows researchers to perform extensive offline simulations, training, and optimization without the constraints of physical hardware availability. Analogous to a digital simulator software that mirrors a complex “real machine,” DT-OCS enables extensive task development and parameter tuning within a virtual environment, dramatically decoupling software development from hardware dependency. Consequently, optimized parameters validated digitally can be seamlessly transferred back to the physical system for deployment, bypassing numerous iterative hardware trials.
The implications of DT-OCS extend well beyond mere time savings. By effectively creating a “digital development toolkit” for optical computing, this framework revolutionizes the research ecosystem—transforming optical computing platforms from isolated, hardware-bound experiments to versatile, shareable research infrastructures. Researchers can now conduct task training, performance benchmarking, and method comparisons entirely within a unified digital realm, fostering collaborative innovation. Distinguished from legacy OCS paradigms, DT-OCS supports parallel task development workflows, allowing multiple computational problems to be advanced simultaneously without hardware conflicts. This capability markedly enhances flexibility, reduces development bottlenecks, and accelerates the maturation and practical adoption of optical computing technologies.
Envisioning the trajectory of optical computing, the integration of digital twin models with physical hardware appears indispensable. Contemporary transportation systems, for instance, benefit from the synergy between tangible road networks and dynamic digital mapping platforms. Similarly, next-generation optical computing platforms should embody dual representations: a robust physical computing infrastructure supplemented by perpetually updated digital twins. This paradigm champions accessibility, reproducibility, and scalability—cornerstones for fostering broad-scale collaboration. It paves the way for unified validation standards and equitable performance comparisons, catalyzing optical computing’s evolution into a general-purpose, widely deployable resource rather than a niche experimental setup.
The DT-OCS framework’s hallmark is its strategic decoupling of task development from hardware constraints. In traditional optical computing, task training and parameter fine-tuning necessitate iterative hardware engagements involving adjustments, diagnostics, and recalibrations. This approach encumbers the process with inefficiencies and precludes simultaneous multi-task development. DT-OCS obviates these impediments by faithfully modeling the physical system’s responses across parameter spectra, enabling exhaustive offline optimization. This digital-first workflow increases research agility, minimizes hardware occupancy, and substantially compresses the development timeline. Consequently, DT-OCS amplifies the throughput and adaptability of optical computing research endeavors.
The real-world efficacy of the DT-OCS framework has been experimentally validated using a cutting-edge high-speed optical computing system incorporating silicon photonic feature-computing chips. These empirical studies demonstrated DT-OCS applications in diverse computational domains, including image classification and sequential decision-making. Notably, configurations optimized within the digital twin translated flawlessly to the physical hardware, with observed task performance closely mirroring digital forecasts. This underscores not only the high fidelity of the DT-OCS model but also its robust transferability across practical scenarios. Moreover, by enabling parallel task development within the digital domain, DT-OCS expedites the overall research workflow, markedly elevating efficiency.
An illustrative application of the DT-OCS system involved offline training and deployment for the Fashion-MNIST image classification task—a benchmark dataset widely used in machine learning. This practical demonstration affirms DT-OCS’s capacity to bridge digital model development with real-world optical computing implementations. Beyond efficiency gains, DT-OCS signifies a conceptual shift toward disentangling computational task design from the idiosyncrasies of physical system constraints. Historically, optical computing research has been hamstrung by its dependence on specific hardware platforms and accessibility limitations, hindering reproducibility and cross-task comparisons. The introduction of an open-source digital twin framework surmounts these barriers by democratizing access and standardizing evaluation protocols.
By openly releasing the DT-OCS framework alongside associated task datasets, the research fosters a community-driven ecosystem where software-based task design, training, and validation can proceed independently of physical system constraints. This openness engenders scalability, reproducibility, and collaborative potential that traditional optical computing architectures cannot easily achieve. Researchers worldwide gain the freedom to explore broader task horizons, perform comprehensive benchmarking, and validate innovative approaches within a consistent computational substrate. Such a paradigm shift propels optical computing from isolated experimental configurations into accessible and extensible platforms, expediting technological advancements and practical deployments.
This pioneering work advocates a transformative application paradigm for optical computing platforms: the symbiotic coexistence of physical hardware and computationally equivalent open-source digital twin models. Only by embracing such dual-system architectures can the field transcend limitations imposed by experimental variability and hardware scarcity. The resultant platforms will be shareable, replicable, and adaptable to a diverse array of research challenges. As optical computing moves towards becoming a mainstream computational resource, the principles embodied by DT-OCS may well establish the foundational infrastructure that underpins scalable, collaborative innovation in photonic information processing.
Subject of Research: Not applicable
Article Title: Digital twin optical computing system
A decade ago, AMD added a protection to its high-end CPUs to protect them against cold boot attacks and other types of physical exploits that siphon sensitive data out of the connected memory chips. Short for Transparent Secure Memory Encryption, TSME encrypts the entire contents stored in memory, making the data useless to physical attackers.
Over time, AMD added TSME to lower-end processors, including the consumer version of its Ryzen chips, a CPU that costs less than the Pro version. Over the years, users of these lower-end chips have gotten used to the added security. Recently and without warning or notice, this lower-end line of AMD chips suddenly dropped the protection, and did so in a way that was impossible to detect on Windows machines and required a fair amount of technical work when using Linux.
Now you see it, now you don't
AMD has yet to say why TSME worked on these CPUs, or even to confirm the change. AMD declined to answer questions sent by email other than to say TSME "is a security feature only applied to PRO CPUs as part of AMD PRO Technologies." The statement is the first known time the chipmaker has explicitly made this restriction public.
Intel is invading the physical AI space with a reentry into the robotics market it quit many years ago amid financial struggles.
The robotics strategy is part of the company’s larger plan to establish AI on the “edge,” in which devices have the computing capability to run AI locally. Many devices lack AI capabilities and have to offload processing to the cloud.
The chipmaker said its Intel Series 3 processors are now in 130 edge AI and robotics designs. It also had a design win with SensoryAI, which provides technology for robots that include Ella, a robotic barista made by Crown Digital.
The company’s Core Ultra Series 3 processors are derivatives of chip designs intended for laptops. But Intel has achieved a level of power efficiency for long battery life that allows those chips to be adapted for handheld devices and laptops.
Intel also said it can build advanced robotics chips thanks to its latest manufacturing technologies.
For example, many robotic functions, such as computer vision and real-time controls, can be integrated into a single chip. Previously, functions like graphics and movement and control were distributed among different cores in a chip.
SensoryAI, for example, has a chip architecture that provides the robotic barista — which is more like a robotic arm — with AI capabilities, Intel said.
The main “Avatar” agent handles customers as the main “Ella” agent reasons and executes the task. If Ella encounters errors, it passes on the issue to a Guardian agent, which helps with the recovery. Some issues could include making sense of an order, or cups that might be stuck.
The three agents are embedded in a single piece of Core Ultra Series 3 silicon.
Intel is displaying some of those robots at the Computex trade show in Taiwan. The company shared a video of a humanoid-style robot from the floor in a X.com post
This is not Intel’s first attempt at the robotics market. Intel sold robotics chips and kits when it was a dominant chip player in the field, but curtailed efforts in 2021 after Pat Gelsinger took over as CEO and restructured the company to focus on manufacturing.
Robotics is now back on the menu under new Intel CEO Lip-Bu Tan, who replaced Gelsinger last year. He has restructured to company to focus on high-growth areas that can generate high returns.
A Morgan Stanley study last year indicated the robotics market could be worth $5 trillion by 2050 — and more than 1 billion humanoid robots could be in operation.
However, challenges remain. There isn’t yet enough real-world data to train robots to do targeted work. And the AI models — generally called world models — they will need are still under development.
Training robots to do a specific job requires a sequence of events to happen in succession without any errors. Companies are still training robots to spot and understand errors, analyze possible resolutions, and take the right corrective action.
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