Intekplus will supply about 6 billion won worth of semiconductor and substrate inspection equipment overseas.

Intekplus said in a regulatory filing on Sept. 9 that it signed a contract with ACCUTECH to supply semiconductor and substrate inspection equipment. ACCUTECH is a semiconductor equipment distributor based in Shenzhen, China.

The contract is valued at about 6.08 billion won, equivalent to 6.78% of Intekplus’ 98.77 billion won in revenue last year.

Intekplus will supply two types of equipment from its iPIS series for semiconductor package and chip inspection and its iSIS series for semiconductor mid-end and substrate inspection. The specific models were not disclosed.

The iPIS lineup includes systems for final visual defect inspection of semiconductor packages, 3D dimensional inspection and 2D side inspection. The iSIS lineup includes systems for 3D inspection of microbumps on flip-chip substrates and 3D inspection of bumps and surface defects on flip-chip ball grid array (FC-BGA) substrates.

Payments will be made in four stages. Intekplus will receive 30% of the contract value as an advance payment and another 30% after equipment delivery. A further 30% will be paid after installation and commissioning are verified, with the remaining 10% due after final acceptance. The contract runs through Nov. 30 next year, with the final payment expected before then.

Intekplus recently won an order from a major Japanese substrate manufacturer for automated optical inspection (AOI) equipment used in glass-substrate research and development. The equipment will be delivered in the second half of this year. The number of systems and contract value were not disclosed.

Intekplus posted first-half revenue of 21.77 billion won and an operating loss of 7.03 billion won. Its first-half net loss widened from a year earlier to 7.54 billion won.

U.S. semiconductor equipment maker Axcelis Technologies said Sept. 8 it plans to build a new equipment manufacturing facility in South Korea with an investment of about $35 million.

Robert Mahoney, Axcelis' Executive Vice President of Global Operations, recently participated in an investment declaration ceremony in Washington, D.C., with officials from South Korea's Ministry of Trade, Industry and Resources (MOTIR) and the Korea Trade-Investment Promotion Agency (KOTRA). The investment totals $35 million.

The new manufacturing facility will be built in Pyeongtaek with a total gross floor area of about 200,000 square feet. The investment is aimed at expanding ion implantation equipment production capacity to meet global demand.

Ion implanters are key front-end semiconductor manufacturing tools that precisely introduce ions into wafers to create desired electrical properties. Axcelis Korea established the Axcelis Asia Operations Center (AAOC) in Pyeongtaek in 2021 and began producing the equipment locally.

The new facility will be designed around a lean manufacturing environment aimed at eliminating waste and maximizing production efficiency. A groundbreaking ceremony is scheduled for Oct. 20, with production targeted to begin in the second half of 2028.

The facility will include Class 1,000 (ISO 6) and Class 10,000 (ISO 7) cleanrooms, a warehouse and a training center. A Class 1,000 cleanroom limits particles measuring 0.5 micrometers (㎛) to no more than 1,000 per cubic foot.

"Ion implanters are among the most important tools in front-end semiconductor manufacturing," Axcelis President and Chief Executive Officer Russell Low said. The investment will strengthen the company's global high-volume manufacturing infrastructure and expand the capabilities needed to serve customers worldwide, he said.

Qualcomm has announced a semiconductor partnership with Amazon for artificial intelligence data centers, tied to warrants and a potential deal worth up to $60 billion.

Qualcomm said Sept. 8 it began a product collaboration with Amazon to build next-generation AI data center infrastructure. The partnership aims to supply cost-efficient custom application-specific integrated circuits (ASICs) for large-scale AI inference workloads on Amazon Web Services (AWS). ASICs are dedicated chips optimized for specific computing tasks or services.

"As AI demand accelerates, data center infrastructure will require advances in both computing and connectivity to deliver greater performance with more efficiency," Qualcomm Chief Executive Officer Cristiano Amon said. "Qualcomm is pleased to work with AWS on customized silicon and connectivity solutions, bringing decades of leadership in advanced processing and power-efficient compute, to deliver breakthrough performance and enable the next generation of AI infrastructure."

The companies will also jointly design high-performance optical connectivity solutions to address rising data traffic and bandwidth requirements in data centers. The solutions will target transmission speeds of up to 1.6 terabits per second (Tbps), using Qualcomm's high-speed serializer/deserializer (SerDes) and optical digital signal processor (DSP) technologies.

SerDes chips convert slower parallel signals inside semiconductors into a single high-speed serial data stream for transmission. Optical DSPs precisely compensate for signal distortion and loss as optical data travels through fiber.

Qualcomm Chief Financial Officer Akash Palkhiwala said the Amazon collaboration could generate a potential revenue opportunity of as much as $60 billion. He added that Amazon's selection validates Qualcomm's data center technology, strategy and ability to supply products at scale.

Up to $60 Billion Over 10 Years

The potential revenue cited by Palkhiwala is linked to Qualcomm's issuance of warrants, which give Amazon the right to purchase shares at a specified price in the future. Qualcomm plans to vest the warrants in stages based on Amazon's purchases of its data center ASICs and optical connectivity solutions. Amazon's maximum contracted purchase amount is $60 billion, with the agreement running for 10 years.

Amazon has already secured 15% of the warrants after committing to purchase Qualcomm products at the initial stage of the agreement. The product volume is estimated at about $9 billion.

Qualcomm has also received purchase orders (POs) from Amazon and begun chip production. Revenue from the chips is expected to be recognized starting in December. That makes Qualcomm's previously announced fiscal 2027 data center revenue forecast of about $5 billion increasingly likely to be achieved.

Qualcomm also plans to expand its use of Amazon's AI platform to shorten semiconductor design cycles. The company will increase the use of services including Amazon Bedrock in electronic design automation (EDA) workloads.

EDA involves using software to design semiconductor circuits and verify their performance. Amazon Bedrock is a fully managed generative AI service that allows developers to use pretrained generative AI models in cloud environments for their specific workflows and applications.

Qualcomm's data center ASICs are part of its Dragonfly portfolio. In addition to custom silicon, Dragonfly includes the C1000 central processing unit (CPU), AI300 AI inference accelerator and connectivity products.

Taesung said Sept. 9 it is showcasing glass substrate production equipment technology at the International Semiconductor Substrate & Advanced Packaging Industry Exhibition, or KPCA Show 2026.

KPCA Show is a South Korean exhibition specializing in printed circuit boards (PCBs) and semiconductor packaging. The event is being held Sept. 9-11 at Songdo Convensia in Incheon. Taesung is presenting process technologies optimized for glass substrates, including etching, cleaning and plating, at its booth.

In particular, the company is showcasing key equipment for the Through Glass Via (TGV) process. TGVs are tiny holes formed in glass substrates to create electrical signal paths between chips and substrates. Taesung is displaying etching equipment that shapes and refines the holes, cleaning equipment that removes contaminants and plating equipment that coats the holes with metal to enable electrical conductivity.

Taesung has developed equipment for each stage of glass substrate processing based on technology accumulated in its existing PCB manufacturing equipment business. The company is targeting the market with mass-production solutions tailored to different manufacturing methods and process conditions for individual customers. Supply discussions with major customers are currently in their final stages, and Taesung expects to secure new orders within this month.

"Global demand for glass substrates is growing as AI semiconductors become more powerful and advanced packaging technologies develop," Taesung said. "We will actively showcase our differentiated process equipment technology at KPCA Show."

The growing AI and high-performance computing (HPC) markets are also increasing the importance of next-generation semiconductor packaging technologies. Glass substrates, a next-generation packaging material, have flatter surfaces than conventional substrates made of plastic or organic materials, making them better suited for denser, finer circuit patterns. They are also less susceptible to warpage and deformation caused by heat.

Samsung Electronics said Sept. 9 that it will jointly develop artificial intelligence (AI) models with Mistral AI specialized for semiconductor design and manufacturing.

The two companies formed a strategic partnership on the occasion of the South Korea-France summit held the same day. Samsung previously made a large equity investment in Mistral AI, laying the foundation for long-term technology cooperation and joint business initiatives. The Series D funding round for Mistral AI led by Samsung totaled €3 billion.

The companies will develop semiconductor-specific AI combining semiconductor technology and manufacturing data from Samsung’s Device Solutions (DS) division with Mistral AI’s AI model technology. The specialized AI will be deployed in stages across Samsung’s semiconductor operations, from chip design to manufacturing data analysis, defect prediction and process optimization. The goal is to shorten development time, improve manufacturing efficiency and quality, and enhance productivity and precision across semiconductor operations.

The companies will also jointly build an AI platform and operating system optimized for semiconductor operations using an on-premises approach. On-premises systems are built and operated on a company’s own servers and data centers. The approach is intended to enable Samsung to securely use semiconductor-related data without transferring it outside the company.

Samsung plans to expand its cooperation with Mistral AI across its DS division, from memory to semiconductor foundry and logic businesses. It will also accelerate AI transformation (AX) across all business units. The company ultimately plans to build an AI-based semiconductor ecosystem that can connect customers and partners.

“As the complexity of semiconductor design and manufacturing increases rapidly, the ability to use vast amounts of data securely and precisely through AI is emerging as a key competitive advantage,” said Jun Young-hyun, vice chairman and head of Samsung Electronics’ DS division. “By building AI models and platforms specialized for the semiconductor industry with Mistral AI, we will establish a new standard for AI-driven semiconductor innovation.”

“AI is redefining the creation of advanced technologies, from semiconductors to software,” said Arthur Mensch, co-founder and chief executive officer of Mistral AI. “Through our collaboration with Samsung Electronics, we will contribute to advances in semiconductor design and manufacturing and across the global AI value chain.”

Mistral AI is a French AI company that has developed high-efficiency large language models (LLMs) including Mistral Large. It was founded by AI researchers formerly at Google DeepMind and Meta. The company has technology for building customized on-premises AI models for industries requiring high levels of data security, including finance, manufacturing and energy.

Samsung Electronics plans to become the first in the industry to introduce high-numerical-aperture (High-NA) extreme ultraviolet (EUV) lithography equipment from Dutch semiconductor equipment maker ASML into advanced DRAM manufacturing facilities by 2028. The companies will also jointly develop large 300mm photomasks.

Samsung Electronics announced the expanded cooperation with ASML on next-generation semiconductor manufacturing on Sept. 8.

"Building on the results of our existing cooperation with ASML, we will accelerate the development and adoption of next-generation technologies needed to manufacture advanced artificial intelligence (AI) semiconductors," Samsung said. "The cooperation means High-NA EUV technology is ready for full-scale application in advanced memory, following its use in foundry manufacturing processes."

High-NA refers to a numerical aperture of 0.55, a measure of a lens's ability to collect light. Low-NA EUV equipment has a numerical aperture of 0.33. The improved light-gathering capability allows High-NA systems to print finer and more precise semiconductor circuit patterns than Low-NA equipment.

Samsung plans to use the ultra-fine patterning technology to overcome the limits of DRAM scaling. It also aims to simplify circuit-forming processes and improve productivity.

○ Samsung Joins 300mm Photomask Consortium

Samsung will also participate in a large-mask consortium led by ASML. The consortium was formed to transition the photomask standard for semiconductor lithography equipment to 300mm.

Samsung will play a key role in the transition to 300mm photomasks based on its experience in memory manufacturing and semiconductor foundry production, as well as its track record in EUV operations. Consortium members will jointly review global technology trends in lithography equipment and photomasks.

A photomask is a precision template used to form microscopic electronic circuits on semiconductor wafers. Inside lithography equipment, light is projected through the mask to transfer circuit designs onto a wafer. Patterning precision affects semiconductor computing performance and yield.

The industry has traditionally used 150mm photomasks. With 150mm masks, High-NA EUV equipment has about half the exposure field of Low-NA EUV systems, meaning the area that can be patterned in a single exposure is smaller. Large chip circuits therefore need to be exposed in two sections. This is because the optical system was modified to prevent light interference and shadowing effects.

The separately exposed circuit sections must then be connected through a process known as stitching. Switching to 300mm masks eliminates the stitching constraint. This can reduce process steps, improve productivity and lower chip manufacturing costs. Samsung believes 300mm masks will be necessary to maximize the performance of High-NA EUV equipment in advanced semiconductor manufacturing, where tens of billions of transistors are densely packed onto a chip.

"Samsung Electronics is strengthening its leadership in advanced semiconductor manufacturing, including foundry and memory," said Jun Young-hyun, vice chairman of Samsung Electronics. "By strengthening our cooperation with ASML, we will establish the technology foundation for the next generation of AI."

"Samsung Electronics has long been one of ASML's most important partners, and we have advanced semiconductor manufacturing technology together," said Christophe Fouquet, chief executive officer of ASML. "In the new era driven by AI, we will continue to lead next-generation semiconductor manufacturing innovation together with Samsung Electronics."

The Korea Electronics Packaging and Circuits Association (KPCA) said Sept. 7 that it conducted an advanced semiconductor packaging industry training program in Taiwan.

The Taiwan advanced packaging program was jointly organized by KPCA, Gyeongsang National University and Pukyong National University. A total of 16 people participated, including students specializing in semiconductor packaging, two professors from Gyeongsang National University and two KPCA officials.

The program was designed to give Korean students firsthand experience of the global semiconductor industry and help them understand Taiwan's semiconductor packaging and printed circuit board (PCB) ecosystem. Participants visited copper-clad laminate maker Elite Material Co. (EMC), Lunghwa University of Science and Technology, the Taiwan Printed Circuit Association (TPCA) and SEMICON Taiwan 2026.

EMC is a materials company that produces copper-clad laminates (CCLs), which are used to manufacture PCBs. The visit gave participants an opportunity to observe semiconductor and electronics technologies and production sites. It also helped deepen their understanding of changes in the global supply chain and the direction of the advanced packaging industry.

At Lunghwa University of Science and Technology, participants examined Taiwan's industry-academia cooperation and semiconductor workforce training system. During their visit to TPCA, they learned about Taiwan's PCB and semiconductor packaging industries, global competitiveness, industrial ecosystem and workforce development policies.

At the final stop, SEMICON Taiwan 2026, participants explored the latest technologies and market trends across the global semiconductor industry. They reviewed developments in advanced packaging, high-bandwidth memory (HBM), chiplets and 2.5D and 3D packaging, technologies that are gaining importance amid the rapid growth of artificial intelligence (AI) semiconductors. SEMICON Taiwan is an exhibition for sharing advanced semiconductor technologies.

"For Korea to continue growing as a global semiconductor powerhouse, not only industry but also universities and research institutions need to work together to systematically develop future professionals," KPCA said. "KPCA will expand cooperation with universities, companies and related organizations to cultivate talented professionals who will lead the PCB and semiconductor packaging industries and strengthen global industry-academia collaboration."

KPCA is building a cooperative framework connecting industry, government, universities and research institutions. The effort is aimed at strengthening the competitiveness of Korea's PCB and semiconductor packaging industries and expanding global cooperation.