SK keyfoundry said Sept. 9 it signed a long-term agreement to provide 130-nanometer foundry services to automotive semiconductor company Elmos Semiconductor.

SK keyfoundry recently held a signing ceremony in Frankfurt am Main, Germany, and will provide foundry capacity to Elmos through 2037. Elmos has used SK keyfoundry’s 350-nanometer process technology for the past 18 years.

“Elmos is an outstanding company in the automotive semiconductor market,” an SK keyfoundry official said. “Securing a long-term supply agreement is meaningful not only in terms of revenue but also for our technological growth.”

Wafer supply prices may be adjusted under the agreement. The 200-millimeter wafers supplied by SK keyfoundry are experiencing a global shortage as major chipmakers including TSMC and Samsung Electronics reduce 200-millimeter capacity and shift toward 300-millimeter production.

SK keyfoundry and Elmos will jointly develop the E550.01 Smart 4-Channel eFuse Controller. The chip controls the supply of power inside a vehicle across four separate paths and cuts power to protect electrical systems when abnormalities such as overcurrent occur. Mass production is targeted for 2027.

SK keyfoundry will also provide Elmos with deep trench isolation (DTI) capability. The company said the technology enables highly integrated, high-voltage designs with low substrate current.

“SK keyfoundry has been a trusted partner for many years,” Elmos Chief Executive Officer Arne Schneider said. “It will support our continued growth.”

“We will accelerate our automotive semiconductor supply, starting with Elmos,” SK keyfoundry CEO Lee Dong-jae said.

DB HiTek is in the final stages of preparing for mass production of its 8-inch silicon carbide (SiC) wafer foundry business.

DB HiTek said Sept. 9 that it had completed reliability verification of a 1,200-volt SiC MOSFET. The company plans to provide customers with its third-generation process design kit (PDK) in November as it moves to launch its foundry business.

The third-generation PDK targets specific on-resistance of 2.3 mΩ·cm² at an 18-volt gate voltage, down from 2.5 mΩ·cm² for the second generation. It is also designed to allow the device to withstand a sudden short circuit for 2.5 microseconds without damage. DB HiTek said the third-generation PDK could shorten semiconductor design time by more than a year.

“We have secured the core technology and mass-production foundation for what will be the world’s first 8-inch SiC foundry service,” DB HiTek said. “We will prepare for mass production as planned and move to establish an early lead in the market.”

Mass production is targeted for the first half of next year. Rival SK keyfoundry is also expected to begin mass production of 8-inch SiC foundry products in the first half of next year. SiC foundry operations require production lines to be developed and established jointly with customers, meaning both companies have effectively secured customers ahead of mass production. Samsung Electronics also has an 8-inch SiC production line, but does not offer it to external foundry customers.

The SiC semiconductor market currently centers on 150-millimeter wafers, while mass production using 200-millimeter wafers remains rare globally. SiC semiconductors use specially processed wafers that differ from conventional silicon (Si) wafers. Due to the technology’s lower maturity, production yields for 200-millimeter SiC wafers are lower than for 150-millimeter wafers, resulting in lower output.

DB HiTek will operate its SiC foundry at its Sangwoo Campus in Eumseong, North Chungcheong Province, converting the current development line into a mass-production line. Initial capacity will be relatively small at 800 wafers a month, about 1.3% of the Sangwoo facility’s total monthly capacity of 63,000 wafers. The company has established an integrated process covering design, manufacturing, characterization, reliability verification and epiwafer supply.

For now, DB HiTek is operating the development line primarily for customers it has already secured. It plans to add customers after establishing the mass-production system and gradually expand capacity in line with market demand.

Qualcomm has announced a semiconductor partnership with Amazon for artificial intelligence data centers, tied to warrants and a potential deal worth up to $60 billion.

Qualcomm said Sept. 8 it began a product collaboration with Amazon to build next-generation AI data center infrastructure. The partnership aims to supply cost-efficient custom application-specific integrated circuits (ASICs) for large-scale AI inference workloads on Amazon Web Services (AWS). ASICs are dedicated chips optimized for specific computing tasks or services.

"As AI demand accelerates, data center infrastructure will require advances in both computing and connectivity to deliver greater performance with more efficiency," Qualcomm Chief Executive Officer Cristiano Amon said. "Qualcomm is pleased to work with AWS on customized silicon and connectivity solutions, bringing decades of leadership in advanced processing and power-efficient compute, to deliver breakthrough performance and enable the next generation of AI infrastructure."

The companies will also jointly design high-performance optical connectivity solutions to address rising data traffic and bandwidth requirements in data centers. The solutions will target transmission speeds of up to 1.6 terabits per second (Tbps), using Qualcomm's high-speed serializer/deserializer (SerDes) and optical digital signal processor (DSP) technologies.

SerDes chips convert slower parallel signals inside semiconductors into a single high-speed serial data stream for transmission. Optical DSPs precisely compensate for signal distortion and loss as optical data travels through fiber.

Qualcomm Chief Financial Officer Akash Palkhiwala said the Amazon collaboration could generate a potential revenue opportunity of as much as $60 billion. He added that Amazon's selection validates Qualcomm's data center technology, strategy and ability to supply products at scale.

Up to $60 Billion Over 10 Years

The potential revenue cited by Palkhiwala is linked to Qualcomm's issuance of warrants, which give Amazon the right to purchase shares at a specified price in the future. Qualcomm plans to vest the warrants in stages based on Amazon's purchases of its data center ASICs and optical connectivity solutions. Amazon's maximum contracted purchase amount is $60 billion, with the agreement running for 10 years.

Amazon has already secured 15% of the warrants after committing to purchase Qualcomm products at the initial stage of the agreement. The product volume is estimated at about $9 billion.

Qualcomm has also received purchase orders (POs) from Amazon and begun chip production. Revenue from the chips is expected to be recognized starting in December. That makes Qualcomm's previously announced fiscal 2027 data center revenue forecast of about $5 billion increasingly likely to be achieved.

Qualcomm also plans to expand its use of Amazon's AI platform to shorten semiconductor design cycles. The company will increase the use of services including Amazon Bedrock in electronic design automation (EDA) workloads.

EDA involves using software to design semiconductor circuits and verify their performance. Amazon Bedrock is a fully managed generative AI service that allows developers to use pretrained generative AI models in cloud environments for their specific workflows and applications.

Qualcomm's data center ASICs are part of its Dragonfly portfolio. In addition to custom silicon, Dragonfly includes the C1000 central processing unit (CPU), AI300 AI inference accelerator and connectivity products.

Meta and Panmnesia have proposed a next-generation artificial intelligence (AI) data center architecture designed to make an entire data center operate like a single chip. The approach could address latency problems that emerge as AI models grow larger.

Panmnesia said Sept. 8 that it and Meta introduced technology in a Nature Reviews journal that connects central processing units (CPUs), accelerators and memory through Compute Express Link (CXL) and scales the architecture across a data center. Researchers from Meta and Panmnesia co-authored the paper.

The approach uses CXL to reduce variations in latency between racks, allowing a data center to operate predictably like a single chip. CXL is a high-speed interface that connects different devices including CPUs, graphics processing units (GPUs) and memory.

Racks, the building blocks of AI infrastructure, exchange data rapidly within each rack using high-speed link technologies. Standard interfaces such as Ethernet and InfiniBand are used to connect one rack to another.

The problem is that as AI models expand to trillions of parameters, latency with conventional interfaces increases sharply. AI companies have increased the number of CPUs and GPUs to train on massive datasets, inevitably resulting in higher latency.

Meta and Panmnesia addressed latency variation by connecting racks through CXL. They added three types of hardware: high-fanout switches, fabric controllers and link acceleration units. They also proposed optical CXL to reduce the physical distance over which signals must travel.

The number of accelerators that a single CPU can manage increased from two to 16, while up to 960 connected domains can be managed. Latency was reduced by as much as 90%. Panmnesia said the CXL-based technology demonstrated that models larger than today's AI models can be trained without interruption.

"CXL presents a direction for next-generation AI infrastructure in which a data center operates as a single computing system," Panmnesia CEO Jung Myoungsoo said.

Samsung Electronics said Sept. 9 that it will jointly develop artificial intelligence (AI) models with Mistral AI specialized for semiconductor design and manufacturing.

The two companies formed a strategic partnership on the occasion of the South Korea-France summit held the same day. Samsung previously made a large equity investment in Mistral AI, laying the foundation for long-term technology cooperation and joint business initiatives. The Series D funding round for Mistral AI led by Samsung totaled €3 billion.

The companies will develop semiconductor-specific AI combining semiconductor technology and manufacturing data from Samsung’s Device Solutions (DS) division with Mistral AI’s AI model technology. The specialized AI will be deployed in stages across Samsung’s semiconductor operations, from chip design to manufacturing data analysis, defect prediction and process optimization. The goal is to shorten development time, improve manufacturing efficiency and quality, and enhance productivity and precision across semiconductor operations.

The companies will also jointly build an AI platform and operating system optimized for semiconductor operations using an on-premises approach. On-premises systems are built and operated on a company’s own servers and data centers. The approach is intended to enable Samsung to securely use semiconductor-related data without transferring it outside the company.

Samsung plans to expand its cooperation with Mistral AI across its DS division, from memory to semiconductor foundry and logic businesses. It will also accelerate AI transformation (AX) across all business units. The company ultimately plans to build an AI-based semiconductor ecosystem that can connect customers and partners.

“As the complexity of semiconductor design and manufacturing increases rapidly, the ability to use vast amounts of data securely and precisely through AI is emerging as a key competitive advantage,” said Jun Young-hyun, vice chairman and head of Samsung Electronics’ DS division. “By building AI models and platforms specialized for the semiconductor industry with Mistral AI, we will establish a new standard for AI-driven semiconductor innovation.”

“AI is redefining the creation of advanced technologies, from semiconductors to software,” said Arthur Mensch, co-founder and chief executive officer of Mistral AI. “Through our collaboration with Samsung Electronics, we will contribute to advances in semiconductor design and manufacturing and across the global AI value chain.”

Mistral AI is a French AI company that has developed high-efficiency large language models (LLMs) including Mistral Large. It was founded by AI researchers formerly at Google DeepMind and Meta. The company has technology for building customized on-premises AI models for industries requiring high levels of data security, including finance, manufacturing and energy.

Arm is preparing for the spread of agentic artificial intelligence (AI) across mobile devices, data centers and robotics.

Arm unveiled “CSS for Mobile 2,” its latest compute subsystem (CSS) for mobile devices, on Sept. 7. CSS for Mobile 2 combines the Mali G2 Ultra NX graphics processing unit (GPU) with the C2 CPU Cluster.

The platform is optimized for edge environments as agentic AI evolves. Arm expects agentic AI workloads to increasingly shift from data centers to edge devices such as desktops, laptops and mobile devices, driven by high token costs, long latency and security concerns. The company expects on-device computing, which operates physically closer to users, to become increasingly important in addressing these issues.

The Mali G2 Ultra NX features a dedicated neural accelerator. It supports neural super sampling, which renders graphics at a lower resolution and then uses AI to reconstruct them at a higher resolution, extending technology previously used on desktops to mobile environments. Arm placed the neural accelerator close to the GPU to enable neural graphics at about 1 watt of power on mobile devices. Frame rates can increase by as much as fourfold at the same power level.

The C2 CPU Cluster enhances Scalable Matrix Extension 2 (SME2) capabilities for AI computing. While the previous C1 supported one SME2 unit, the C2 can be configured with up to two. SME2 performance in the C2 reaches 5 to 7 trillion operations per second (TOPS). General CPU performance has also improved, with single-thread performance up 15% and multi-thread performance up 12% from the previous generation. Processing time for agentic AI workloads is reduced by as much as 24%.

Arm also introduced “Neoverse CSS N4” for data centers. The platform is designed to accelerate development of custom systems-on-chip (SoCs) for general-purpose computing, networking and storage. It supports enhanced security, higher memory bandwidth, chiplet interfaces, LPDDR6 and PCIe Gen7. Arm increased design flexibility so customers can configure core counts, cache capacity and input/output (I/O) according to their requirements. Performance per socket is more than double that of the previous generation, while performance per watt improves 25% and memory bandwidth increases 75%.

Arm also provided an update on its first silicon chip, the “AGI CPU,” announced in March. The company said OpenAI, Meta, Cloudflare, Oracle, SAP and Lenovo are developing AGI CPU-based solutions following its launch.

Related products are expected to be released in the coming months. Customers that design their own SoCs can receive the technology as intellectual property (IP), while those seeking to rapidly expand computing infrastructure can choose finished products.

Arm is also strengthening its push into the physical AI market, including autonomous driving, robots and drones. The company estimates the physical AI computing market is currently worth $25 billion and expects it to grow to more than $200 billion after 2030.

Arm also announced the launch of Total Design for Physical AI, with more than 80 key companies including AWS, Hugging Face, NXP, Siemens and Unitree participating. The initiative links the entire development cycle — including silicon, cloud, sensing, security and system validation — with the physical AI ecosystem to support product development. Arm is also developing a common framework for robotics platforms, aiming to rigorously standardize robot capabilities by level, similar to the Level 1-to-5 system used for autonomous driving.

Synopsys is expanding its semiconductor design platform following its acquisition of Ansys, targeting further growth in South Korea’s semiconductor market.

Shankar Krishnamoorthy, chief product development officer (CPDO) at Synopsys, told a press conference at the Grand InterContinental Seoul Parnas in Gangnam on Sept. 8 that the company will “accelerate technological innovation in South Korea through agentic artificial intelligence (AI), multiphysics-based design and a silicon-to-systems integrated engineering approach.”

The importance of the South Korean market is growing. According to Synopsys’ own research, semiconductors are expected to account for 42.3% of the country’s total exports this year, while high-bandwidth memory (HBM) exports are projected to increase 153%.

Most of Synopsys’ revenue in South Korea comes from the memory sector, with Samsung Electronics and SK hynix among its major customers. The two companies use Synopsys’ semiconductor design tools and other technologies to develop memory chips.

Synopsys is also expanding its revenue base into system semiconductors. “Beyond memory, we work with Samsung Electronics’ foundry and System LSI businesses,” Krishnamoorthy said. “We also collaborate with Rebellions and FuriosaAI across all areas, including electronic design automation (EDA) tools.”

Synopsys’ strength lies in the breadth of its design environment. The company acquired engineering simulation software company Ansys in July last year, expanding beyond its existing EDA and intellectual property (IP) portfolio to add system design and simulation capabilities. This allows chips to be designed with consideration for the systems in which they will operate, including rockets, aircraft and data centers.

The company is also addressing the growing complexity of AI chip design. As AI chips incorporate more dies and HBM, interconnect density increases, requiring designers to consider signal integrity, power, thermal effects and stress simultaneously. Synopsys combines EDA and multiphysics technologies to support advanced designs including three-dimensional integrated circuits (3D ICs) and co-packaged optics (CPO).

Synopsys is also applying agentic AI to EDA. The technology assists engineers and autonomously performs lengthy tasks. In an agentic AI design verification process with Nvidia, the time required to obtain register-transfer level (RTL) results was reduced by a factor of 50, while verification coverage increased 20%. Productivity in analog and mixed-signal design improved by as much as threefold.

Synopsys also supports its own application programming interface (API). The company said it requires fewer tokens and lower token costs than competing solutions while significantly reducing latency.

SEMIFIVE has secured its first mass-production project using a 4-nanometer process. The company did not disclose the size of the supply deal, but said it exceeds 10% of last year's revenue of about 121 billion won.

SEMIFIVE said Sept. 8 that it will begin mass production of a 4nm chip for South Korean fabless semiconductor company HyperAccel. Production has been delayed by two quarters from the original schedule. In 2024, SEMIFIVE said it would design HyperAccel's "Bertha" using Samsung Electronics' 4nm process, with mass production initially targeted for the first quarter of 2026.

The company did not disclose the contract value due to a non-disclosure agreement (NDA) with the customer. The deal exceeded 10% of last year's revenue, making it subject to regulatory disclosure. The contract runs through June 15, 2028. Revenue will be recognized in stages as products are supplied, with a 10% upfront payment, 60% interim payment and 30% final payment.

Bertha is specialized for artificial intelligence (AI) inference workloads, including large language models (LLMs). The chip has a die area of more than 500 square millimeters. Naver Cloud is reportedly a potential customer.

As a design house, SEMIFIVE designed Bertha for optimization with Samsung Electronics' semiconductor foundry process. It handled front-end design, verification, packaging, testing and mass production on a turnkey basis. Under the contract, SEMIFIVE generates revenue each time the jointly designed chip is produced.

SEMIFIVE's mass-production orders totaled about 42.3 billion won in the first half of this year, roughly double the 21.2 billion won recorded last year.

"We will continue the growth in mass-production revenue demonstrated in the first half into the second half," SEMIFIVE CEO Cho Myung-hyun said. The company expects revenue to exceed 200 billion won this year. Company-wide revenue totaled about 94.7 billion won in the first half.

Samsung Electronics plans to become the first in the industry to introduce high-numerical-aperture (High-NA) extreme ultraviolet (EUV) lithography equipment from Dutch semiconductor equipment maker ASML into advanced DRAM manufacturing facilities by 2028. The companies will also jointly develop large 300mm photomasks.

Samsung Electronics announced the expanded cooperation with ASML on next-generation semiconductor manufacturing on Sept. 8.

"Building on the results of our existing cooperation with ASML, we will accelerate the development and adoption of next-generation technologies needed to manufacture advanced artificial intelligence (AI) semiconductors," Samsung said. "The cooperation means High-NA EUV technology is ready for full-scale application in advanced memory, following its use in foundry manufacturing processes."

High-NA refers to a numerical aperture of 0.55, a measure of a lens's ability to collect light. Low-NA EUV equipment has a numerical aperture of 0.33. The improved light-gathering capability allows High-NA systems to print finer and more precise semiconductor circuit patterns than Low-NA equipment.

Samsung plans to use the ultra-fine patterning technology to overcome the limits of DRAM scaling. It also aims to simplify circuit-forming processes and improve productivity.

○ Samsung Joins 300mm Photomask Consortium

Samsung will also participate in a large-mask consortium led by ASML. The consortium was formed to transition the photomask standard for semiconductor lithography equipment to 300mm.

Samsung will play a key role in the transition to 300mm photomasks based on its experience in memory manufacturing and semiconductor foundry production, as well as its track record in EUV operations. Consortium members will jointly review global technology trends in lithography equipment and photomasks.

A photomask is a precision template used to form microscopic electronic circuits on semiconductor wafers. Inside lithography equipment, light is projected through the mask to transfer circuit designs onto a wafer. Patterning precision affects semiconductor computing performance and yield.

The industry has traditionally used 150mm photomasks. With 150mm masks, High-NA EUV equipment has about half the exposure field of Low-NA EUV systems, meaning the area that can be patterned in a single exposure is smaller. Large chip circuits therefore need to be exposed in two sections. This is because the optical system was modified to prevent light interference and shadowing effects.

The separately exposed circuit sections must then be connected through a process known as stitching. Switching to 300mm masks eliminates the stitching constraint. This can reduce process steps, improve productivity and lower chip manufacturing costs. Samsung believes 300mm masks will be necessary to maximize the performance of High-NA EUV equipment in advanced semiconductor manufacturing, where tens of billions of transistors are densely packed onto a chip.

"Samsung Electronics is strengthening its leadership in advanced semiconductor manufacturing, including foundry and memory," said Jun Young-hyun, vice chairman of Samsung Electronics. "By strengthening our cooperation with ASML, we will establish the technology foundation for the next generation of AI."

"Samsung Electronics has long been one of ASML's most important partners, and we have advanced semiconductor manufacturing technology together," said Christophe Fouquet, chief executive officer of ASML. "In the new era driven by AI, we will continue to lead next-generation semiconductor manufacturing innovation together with Samsung Electronics."

The Korea Electronics Packaging and Circuits Association (KPCA) said Sept. 7 that it conducted an advanced semiconductor packaging industry training program in Taiwan.

The Taiwan advanced packaging program was jointly organized by KPCA, Gyeongsang National University and Pukyong National University. A total of 16 people participated, including students specializing in semiconductor packaging, two professors from Gyeongsang National University and two KPCA officials.

The program was designed to give Korean students firsthand experience of the global semiconductor industry and help them understand Taiwan's semiconductor packaging and printed circuit board (PCB) ecosystem. Participants visited copper-clad laminate maker Elite Material Co. (EMC), Lunghwa University of Science and Technology, the Taiwan Printed Circuit Association (TPCA) and SEMICON Taiwan 2026.

EMC is a materials company that produces copper-clad laminates (CCLs), which are used to manufacture PCBs. The visit gave participants an opportunity to observe semiconductor and electronics technologies and production sites. It also helped deepen their understanding of changes in the global supply chain and the direction of the advanced packaging industry.

At Lunghwa University of Science and Technology, participants examined Taiwan's industry-academia cooperation and semiconductor workforce training system. During their visit to TPCA, they learned about Taiwan's PCB and semiconductor packaging industries, global competitiveness, industrial ecosystem and workforce development policies.

At the final stop, SEMICON Taiwan 2026, participants explored the latest technologies and market trends across the global semiconductor industry. They reviewed developments in advanced packaging, high-bandwidth memory (HBM), chiplets and 2.5D and 3D packaging, technologies that are gaining importance amid the rapid growth of artificial intelligence (AI) semiconductors. SEMICON Taiwan is an exhibition for sharing advanced semiconductor technologies.

"For Korea to continue growing as a global semiconductor powerhouse, not only industry but also universities and research institutions need to work together to systematically develop future professionals," KPCA said. "KPCA will expand cooperation with universities, companies and related organizations to cultivate talented professionals who will lead the PCB and semiconductor packaging industries and strengthen global industry-academia collaboration."

KPCA is building a cooperative framework connecting industry, government, universities and research institutions. The effort is aimed at strengthening the competitiveness of Korea's PCB and semiconductor packaging industries and expanding global cooperation.