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The post Snapdragon Reality Elite são a nova aposta para óculos XR, com até 48 TOPS de IA e visão de 4,4K por olho appeared first on Tek Notícias.

Artificial intelligence is transforming the world, but it also comes with a growing energy problem. Modern AI systems require enormous computing power, and the powerful chips that perform these calculations generate huge amounts of heat. Keeping these chips cool has become one of the biggest challenges facing the technology industry. Researchers at the Korea Advanced […]

The post New water-cooling technology could make AI chips 10 times more energy efficient appeared first on Knowridge Science Report.

In the relentless quest to push the boundaries of semiconductor technology, researchers from the National University of Singapore (NUS) in collaboration with Applied Materials have unveiled a groundbreaking advancement that promises to reshape the future of microchip manufacturing. As the global semiconductor market races towards the trillion-dollar mark propelled by demand for faster computing, smarter artificial intelligence, and more compact electronic devices, addressing fundamental physical constraints in chip architecture has become a critical imperative. A newly developed atom-thin coating — a monolayer of crystalline tungsten disulfide (WS₂) — presents a transformative solution, elegantly overcoming a pressing bottleneck in chip miniaturization with profound implications for speed, reliability, and efficiency.

Traditional transistor miniaturization has long driven performance gains in integrated circuits. However, as transistors and their connecting copper wires shrink into the sub-10 nanometer regime, the surrounding protective layers—essential for maintaining electrical integrity—resist further reduction. These layers, typically tantalum-based barrier and liner materials, must maintain a minimum thickness of around four nanometers. In future nanoscale interconnects, these coatings may consume nearly half the cross-sectional area of the copper wiring, severely throttling electrical conductivity and device speed. The NUS and Applied Materials team’s innovation resides in synthesizing an ultrathin WS₂ film, less than a nanometer thick, that simultaneously fulfills the dual role of barrier and liner, drastically slashing thickness without compromising performance.

This pioneering coating, grown on industry-standard 200-millimeter silicon wafers using a low-temperature thermal atomic layer deposition process at 350 degrees Celsius, exemplifies a remarkable confluence of scalability and compatibility. The process avoids plasma, guaranteeing conformal deposition with precise thickness control down to a single atomic layer. Notably, this method achieves uniform coverage in high aspect ratio trenches, exceeding 95% conformity even at depth-to-width ratios of 10:1. Such attributes position this WS₂ monolayer as a viable drop-in replacement within existing semiconductor fabrication lines, bridging the formidable divide between laboratory breakthroughs and industrial applicability.

The WS₂ film’s threshold thickness of approximately 0.7 nanometers contrasts starkly with the conventional six nanometer standard, enabling a future 20-nanometer-wide copper wire to retain over 90% of its conductive cross-section. This relatively unobstructed copper path translates into reduced electrical resistance and elevated current carrying capacity, directly enhancing chip speed and energy efficiency. Extensive electrical testing demonstrated a monumental reduction in resistance—exceeding a factor of one million—compared to uncoated counterparts. The superior adhesion properties offered by the WS₂ liner promote smooth and continuous copper film formation, vital for producing reliable, defect-free interconnects at such ultrathin dimensions.

Beyond adhesion, the WS₂ monolayer serves as a robust diffusion barrier that impedes copper migration into silicon and dielectric materials under thermal and electrical stress. In accelerated aging tests, conventional barrier-free copper rapidly reacted with underlying silicon, forming deleterious intermetallic compounds and defect clusters. In stark contrast, WS₂-coated samples exhibited no such degradation, maintaining pristine interfaces even after prolonged exposure. Remarkably, devices using the atomically thin barrier exhibited projected lifetimes surpassing unprotected designs by an order of magnitude, signaling a dramatic leap in device durability.

Central to the WS₂ film’s efficacy is its polycrystalline structure composed of myriad tiny grains and grain boundaries arranged in random orientations. Unlike continuous single crystals, where aligned grain boundaries can form direct diffusion channels, the staggered grain orientation in multilayer WS₂ films creates a complex labyrinth that frustrates copper atom penetration akin to the staggered offsets in a well-built brick wall. This insight, derived from computational modeling by NUS chemists, identifies nanoscale grain architecture as a key parameter in optimizing barrier functionality, challenging the entrenched paradigm that perfect crystallinity is always advantageous.

The discovery that a single atomic layer can supplant the combined barrier and liner stack confronts long-held assumptions in semiconductor interconnect design. Prior industry standards dictated separate layers with cumulative thicknesses of several nanometers to provide necessary protection and adhesion. By collapsing these essential roles into an atomically thin WS₂ sheet, researchers open new vistas for continuing Moore’s Law scaling into unprecedented regimes. Professor Silvija Gradečak, co-director of the NUS-Applied Materials Corporate Lab, emphasizes that this fundamental shift in approach heralds a new class of interconnect architectures tailored to atomically precise materials engineering.

The process’s compatibility with low thermal budgets—vital for avoiding damage to complex multilayer device stacks—and its wafer-scale uniformity underscore its readiness for integration into contemporary manufacturing ecosystems. These breakthrough properties allow semiconductor producers to adopt WS₂-based coatings without extensive equipment overhauls or processing disruptions, facilitating rapid technology transfer. Dr. Hippolyte Astier highlights that such advancements transcend the immediate generation of chips, positioning the industry to harness this technology across multiple forthcoming innovations extending out to 2037 and beyond.

Applied Materials’ Director of Engineering, Dr. John Sudijono, notes the criticality of merging academic ingenuity with industrial constraints through the Corporate Lab framework. The collaborative environment enabled iterative validation of WS₂ films under realistic fabrication conditions, ensuring the material meets demanding reliability, scalability, and process compatibility benchmarks. This convergence of theory, experimentation, and commercialization is essential to bridging the notorious gulf between laboratory demonstrations and full-scale production deployments in semiconductor manufacturing.

Looking forward, the team is exploring refined control over WS₂ grain orientation and microscopic interface phenomena to fine-tune long-term stability and electrical behavior. Further studies aim to exploit the low-temperature vapor-phase growth technique to deposit other two-dimensional materials within diverse chip components, expanding the scope of atomic-scale coatings in integrated circuit design. This foundational research not only sets a new standard for interconnect barriers and liners but also signals the inception of a broader materials revolution in microelectronics.

The ultrathin WS₂ monolayer innovation thus represents a monumental stride towards sustaining the pace of semiconductor evolution. By ingeniously combining barrier and liner functionality into a single atomic layer with industrially scalable fabrication, this discovery resolves a pressing miniaturization bottleneck, empowering the continuation of chip performance scaling in an era where every nanoscale dimension counts. As the semiconductor industry confronts the ultimate physical limits of transistor and interconnect shrinking, atomically precise materials like WS₂ will be vital enablers of future computational breakthroughs, underpinning the technology transformations of tomorrow.

Subject of Research: Not applicable

Article Title: Low-temperature wafer-scale growth of ultrathin tungsten disulfide for bifunctional interconnect barriers and liners

News Publication Date: 31-Mar-2026

Web References: https://doi.org/10.1038/s41928-026-01592-6

Image Credits: College of Design and Engineering, NUS

Keywords

Semiconductors, Microelectronics, Materials engineering, Materials science

In a groundbreaking development that could revolutionize the field of artificial intelligence and neuromorphic computing, researchers have unveiled a novel algorithm–hardware co-design approach featuring neuromorphic networks supported by dual memory pathways. This innovative framework, recently published in Nature Machine Intelligence, promises to overcome longstanding challenges in efficiently mimicking brain-like processing in silicon hardware. The fusion of algorithmic design and hardware architecture epitomizes a synergistic leap forward for neuromorphic systems, which strive to emulate the efficiency and adaptability of biological neural networks.

Neuromorphic computing, inspired by the structure and function of the human brain, seeks to replicate neural dynamics through specialized hardware that inherently supports parallel and event-driven processing. Unlike traditional von Neumann architectures, which segregate memory and processing units, neuromorphic systems integrate these functions, drastically reducing latency and energy consumption. However, a persistent limitation in current neuromorphic implementations lies in their constrained memory capacity and difficulties in sustaining stable learning over time. The new co-design method directly confronts these issues by introducing a dual memory pathway mechanism akin to the human brain’s approach to memory storage and retrieval.

The dual memory pathways conceptualized by the research team separate short-term and long-term memory processing within the neuromorphic network. Short-term memory pathways facilitate rapid, flexible adaptation to incoming data, echoing the brain’s working memory functions. Concurrently, long-term memory pathways enable the consolidation and retention of learned information over extended periods. This bifurcation fosters an architectural efficiency that mitigates memory interference and catastrophic forgetting—two notorious hurdles in neuromorphic learning systems and artificial intelligence at large.

Fundamentally, the innovative algorithm tailors synaptic plasticity dynamics to the hardware substrate, leading to more stable, biologically plausible learning rules. The researchers employ spike-timing-dependent plasticity (STDP) paradigms adjusted dynamically by the dual pathways, allowing the system to adapt continuously yet retain core learned information without overwriting. This hybrid plasticity approach is supported by circuits that facilitate separate yet interactive memory stores, closely emulating the hippocampus-neocortex complementarity observed in mammalian brains.

Critically, the design is optimized to leverage emerging non-volatile memory technologies such as resistive RAM (ReRAM), which afford dense, low-power synaptic implementation. The team’s hardware prototype integrates these resistive elements into the dual memory architecture, striking a delicate balance between speed, retention, and energy efficiency. By co-optimizing the algorithmic parameters with hardware constraints, the design attains a level of performance and scalability previously unattainable in neuromorphic networks.

Extensive benchmarking on machine learning tasks highlights the superiority of this co-design approach. Tasks demanding continual learning and domain adaptation—traditionally challenging due to interference effects—exhibit enhanced stability and precision. Notably, the dual pathways enable the neuromorphic system to segregate novel information from prior knowledge efficiently, supporting lifelong learning scenarios critical for real-world AI applications such as robotics, autonomous systems, and adaptive sensory processing.

The implications of this breakthrough extend beyond traditional AI. By more faithfully replicating the brain’s memory consolidation processes, these neuromorphic networks could yield insights into neurological disorders characterized by memory dysfunction. Additionally, the modularity of the dual memory pathways invites future customization and specialization for domain-specific tasks, envisioning a new class of adaptive hardware that evolves alongside its operational environment.

Moreover, the research addresses the formidable challenge of hardware variability and noise—a persistent bottleneck in neuromorphic device deployment. The co-designed algorithm inherently compensates for device-level imperfections through adaptive learning thresholds and redundancy in memory representations. This robustness not only ensures reliable operation over extended periods but also enhances manufacturability and cost-effectiveness for large-scale silicium implementations.

This co-design paradigm exemplifies a pivotal shift in neuromorphic engineering, moving away from generic algorithm deployment on fixed hardware towards integrated development of systems where both hardware and software are mutually optimized. This approach reflects an emerging philosophy in AI hardware: embracing the interdependence of physical substrate and algorithmic function to unlock previously constrained capabilities.

Such a sophisticated neuromorphic platform provokes exciting questions regarding the future landscape of artificial intelligence. Could dual memory pathways represent a standard architectural motif underpinning all next-generation AI chips? Might this design accelerate the creation of truly autonomous systems capable of continuous, context-aware learning within dynamic environments? The potential scale and impact of these mechanisms suggest transformative ripples across industry sectors reliant on AI, from healthcare and finance to autonomous vehicles and beyond.

While promising, challenges remain. Scaling the dual memory network to extremely large, brain-scale systems presents engineering complexities necessitating further innovations in materials, circuit design, and integration techniques. Additionally, fine-tuning the balance between memory consolidation and plasticity, ensuring both adaptability and stability, demands deeper theoretical understanding informed by neuroscience. Continued collaboration between multidisciplinary teams of neuroscientists, material scientists, electrical engineers, and computer scientists will be pivotal to this endeavor.

Looking ahead, this work may catalyze the proliferation of neuromorphic devices poised to operate at unprecedented energy efficiencies while offering continuous learning capability. By taking inspiration from the brain’s memory architecture and rigorously co-designing compatible hardware, the research ushers in an era where artificial intelligence systems can remember, adapt, and grow with a natural fluidity previously attainable only in biological organisms.

The dual memory pathway design stands as a milestone demonstrating that bridging the algorithm–hardware gap is an indispensable strategy for advancing neuromorphic computing. Its capacity to resolve persistent issues such as catastrophic forgetting and memory interference attests to an elegant merging of biological principles with cutting-edge technology. As AI advances toward greater autonomy and contextual sophistication, innovations like these could form the foundational building blocks of truly intelligent machines.

In sum, the synergy achieved by this algorithm–hardware co-design exemplifies the future of neuromorphic architectures — dynamic, adaptive, and deeply integrated with the physical medium of computation. It heralds a pivotal moment where the dream of brain-inspired computing inches closer to reality, promising devices that do not merely process information, but learn and remember in a resilient and energy-efficient manner akin to the human mind.

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Subject of Research: Algorithm–hardware co-design in neuromorphic networks incorporating dual memory pathways to enhance learning stability and efficiency.

Article Title: Algorithm–hardware co-design of neuromorphic networks with dual memory pathways.

Article References:
Sun, P., Su, Z., Achterberg, J. et al. Algorithm–hardware co-design of neuromorphic networks with dual memory pathways. Nat Mach Intell (2026). https://doi.org/10.1038/s42256-026-01255-3

Image Credits: AI Generated

DOI: https://doi.org/10.1038/s42256-026-01255-3

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